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PDL for FM0+
Version1.0
Peripheral Driverl Library for FM0+
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00001 /******************************************************************************* 00002 * Copyright (C) 2013 Spansion LLC. All Rights Reserved. 00003 * 00004 * This software is owned and published by: 00005 * Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). 00006 * 00007 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 00008 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. 00009 * 00010 * This software contains source code for use with Spansion 00011 * components. This software is licensed by Spansion to be adapted only 00012 * for use in systems utilizing Spansion components. Spansion shall not be 00013 * responsible for misuse or illegal use of this software for devices not 00014 * supported herein. Spansion is providing this software "AS IS" and will 00015 * not be responsible for issues arising from incorrect user implementation 00016 * of the software. 00017 * 00018 * SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, 00019 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 00020 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 00021 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 00022 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 00023 * WARRANTY OF NONINFRINGEMENT. 00024 * SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 00025 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 00026 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 00027 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 00028 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 00029 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 00030 * SAVINGS OR PROFITS, 00031 * EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00032 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR 00033 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 00034 * FROM, THE SOFTWARE. 00035 * 00036 * This software may be replicated in part or whole for the licensed use, 00037 * with the restriction that this Disclaimer and Copyright notice must be 00038 * included with each copy of this software, whether used in part or whole, 00039 * at all times. 00040 */ 00041 /******************************************************************************/ 00055 /******************************************************************************/ 00056 /* Include files */ 00057 /******************************************************************************/ 00058 #include "mfs.h" 00059 00060 #if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) 00061 00067 00068 /******************************************************************************/ 00069 /* Local pre-processor symbols/macros ('#define') */ 00070 /******************************************************************************/ 00071 #define UartInstanceToIndex(Instance) ((uint32_t)Instance - (uint32_t)&UART0)/0x100u 00072 #define CsioInstanceToIndex(Instance) ((uint32_t)Instance - (uint32_t)&CSIO0)/0x100u 00073 #define I2cInstanceToIndex(Instance) ((uint32_t)Instance - (uint32_t)&I2C0)/0x100u 00074 #define LinInstanceToIndex(Instance) ((uint32_t)Instance - (uint32_t)&LIN0)/0x100u 00075 00076 00077 /******************************************************************************/ 00078 /* Global variable definitions (declared in header file with 'extern') */ 00079 /******************************************************************************/ 00080 00082 stc_mfs_instance_data_t m_astcMfsInstanceDataLut[MFS_INSTANCE_COUNT] = 00083 { 00084 #if (PDL_PERIPHERAL_ENABLE_MFS0 == PDL_ON) 00085 { 00086 {&UART0, &CSIO0, &I2C0, &LIN0}, /* pstcInstance */ 00087 { 00088 MfsInitMode, /* MFS initial mode */ 00089 MfsInstanceIndexMfs0, /* MFS0 instance index */ 00090 NULL, /* stcInternData (not initialized yet) */ 00091 } 00092 }, 00093 #endif 00094 #if (PDL_PERIPHERAL_ENABLE_MFS1 == PDL_ON) 00095 { 00096 {&UART1, &CSIO1, &I2C1, &LIN1}, /* pstcInstance */ 00097 { 00098 MfsInitMode, /* MFS initial mode */ 00099 MfsInstanceIndexMfs1, /* MFS1 instance index */ 00100 NULL, /* stcInternData (not initialized yet) */ 00101 } 00102 }, 00103 #endif 00104 #if (PDL_PERIPHERAL_ENABLE_MFS2 == PDL_ON) 00105 { 00106 {&UART2, &CSIO2, &I2C2, &LIN2}, /* pstcInstance */ 00107 { 00108 MfsInitMode, /* MFS initial mode */ 00109 MfsInstanceIndexMfs2, /* MFS2 instance index */ 00110 NULL, /* stcInternData (not initialized yet) */ 00111 } 00112 }, 00113 #endif 00114 #if (PDL_PERIPHERAL_ENABLE_MFS3 == PDL_ON) 00115 { 00116 {&UART3, &CSIO3, &I2C3, &LIN3}, /* pstcInstance */ 00117 { 00118 MfsInitMode, /* MFS initial mode */ 00119 MfsInstanceIndexMfs3, /* MFS3 instance index */ 00120 NULL, /* stcInternData (not initialized yet) */ 00121 00122 } 00123 }, 00124 #endif 00125 #if (PDL_PERIPHERAL_ENABLE_MFS4 == PDL_ON) 00126 { 00127 {&UART4, &CSIO4, &I2C4, &LIN4}, /* pstcInstance */ 00128 { 00129 MfsInitMode, /* MFS initial mode */ 00130 MfsInstanceIndexMfs4, /* MFS4 instance index */ 00131 NULL, /* stcInternData (not initialized yet) */ 00132 } 00133 }, 00134 #endif 00135 #if (PDL_PERIPHERAL_ENABLE_MFS5 == PDL_ON) 00136 { 00137 {&UART5, &CSIO5, &I2C5, &LIN5}, /* pstcInstance */ 00138 { 00139 MfsInitMode, /* MFS initial mode */ 00140 MfsInstanceIndexMfs5, /* MFS5 instance index */ 00141 NULL, /* stcInternData (not initialized yet) */ 00142 } 00143 }, 00144 #endif 00145 #if (PDL_PERIPHERAL_ENABLE_MFS6 == PDL_ON) 00146 { 00147 {&UART6, &CSIO6, &I2C6, &LIN6}, /* pstcInstance */ 00148 { 00149 MfsInitMode, /* MFS initial mode */ 00150 MfsInstanceIndexMfs6, /* MFS6 instance index */ 00151 NULL, /* stcInternData (not initialized yet) */ 00152 } 00153 }, 00154 #endif 00155 #if (PDL_PERIPHERAL_ENABLE_MFS7 == PDL_ON) 00156 { 00157 {&UART7, &CSIO7, &I2C7, &LIN7}, /* pstcInstance */ 00158 { 00159 MfsInitMode, /* MFS initial mode */ 00160 MfsInstanceIndexMfs7, /* MFS7 instance index */ 00161 NULL, /* stcInternData (not initialized yet) */ 00162 } 00163 }, 00164 #endif 00165 #if (PDL_PERIPHERAL_ENABLE_MFS8 == PDL_ON) 00166 { 00167 {&UART8, &CSIO8, &I2C8, &LIN8}, /* pstcInstance */ 00168 { 00169 MfsInitMode, /* MFS initial mode */ 00170 MfsInstanceIndexMfs8, /* MFS8 instance index */ 00171 NULL, /* stcInternData (not initialized yet) */ 00172 } 00173 }, 00174 #endif 00175 #if (PDL_PERIPHERAL_ENABLE_MFS9 == PDL_ON) 00176 { 00177 {&UART9, &CSIO9, &I2C9, &LIN9}, /* pstcInstance */ 00178 { 00179 MfsInitMode, /* MFS initial mode */ 00180 MfsInstanceIndexMfs9, /* MFS9 instance index */ 00181 NULL, /* stcInternData (not initialized yet) */ 00182 } 00183 }, 00184 #endif 00185 #if (PDL_PERIPHERAL_ENABLE_MFS10 == PDL_ON) 00186 { 00187 {&UART10, &CSIO10, &I2C10, &LIN10}, /* pstcInstance */ 00188 { 00189 MfsInitMode, /* MFS initial mode */ 00190 MfsInstanceIndexMfs10, /* MFS10 instance index */ 00191 NULL, /* stcInternData (not initialized yet) */ 00192 } 00193 }, 00194 #endif 00195 #if (PDL_PERIPHERAL_ENABLE_MFS11 == PDL_ON) 00196 { 00197 {&UART11, &CSIO11, &I2C11, &LIN11}, /* pstcInstance */ 00198 { 00199 MfsInitMode, /* MFS initial mode */ 00200 MfsInstanceIndexMfs11, /* MFS11 instance index */ 00201 NULL, /* stcInternData (not initialized yet) */ 00202 } 00203 }, 00204 #endif 00205 #if (PDL_PERIPHERAL_ENABLE_MFS12 == PDL_ON) 00206 { 00207 {&UART12, &CSIO12, &I2C12, &LIN12}, /* pstcInstance */ 00208 { 00209 MfsInitMode, /* MFS initial mode */ 00210 MfsInstanceIndexMfs12, /* MFS12 instance index */ 00211 NULL, /* stcInternData (not initialized yet) */ 00212 } 00213 }, 00214 #endif 00215 #if (PDL_PERIPHERAL_ENABLE_MFS13 == PDL_ON) 00216 { 00217 {&UART13, &CSIO13, &I2C13, &LIN13}, /* pstcInstance */ 00218 { 00219 MfsInitMode, /* MFS initial mode */ 00220 MfsInstanceIndexMfs13, /* MFS13 instance index */ 00221 NULL, /* stcInternData (not initialized yet) */ 00222 } 00223 }, 00224 #endif 00225 #if (PDL_PERIPHERAL_ENABLE_MFS14 == PDL_ON) 00226 { 00227 {&UART14, &CSIO14, &I2C14, &LIN14}, /* pstcInstance */ 00228 { 00229 MfsInitMode, /* MFS initial mode */ 00230 MfsInstanceIndexMfs14, /* MFS14 instance index */ 00231 NULL, /* stcInternData (not initialized yet) */ 00232 } 00233 }, 00234 #endif 00235 #if (PDL_PERIPHERAL_ENABLE_MFS15 == PDL_ON) 00236 { 00237 {&UART15, &CSIO15, &I2C15, &LIN15}, /* pstcInstance */ 00238 { 00239 MfsInitMode, /* MFS initial mode */ 00240 MfsInstanceIndexMfs15, /* MFS15 instance index */ 00241 NULL, /* stcInternData (not initialized yet) */ 00242 } 00243 }, 00244 #endif 00245 }; 00246 00247 /******************************************************************************/ 00248 /* Local type definitions ('typedef') */ 00249 /******************************************************************************/ 00250 00251 /******************************************************************************/ 00252 /* Local function prototypes ('static') */ 00253 /******************************************************************************/ 00254 static stc_mfs_intern_data_t* MfsUartGetInternDataPtr(volatile stc_mfsn_uart_t* pstcMfs); 00255 static stc_mfs_intern_data_t* MfsCsioGetInternDataPtr(volatile stc_mfsn_csio_t* pstcMfs); 00256 static stc_mfs_intern_data_t* MfsI2cGetInternDataPtr(volatile stc_mfsn_i2c_t* pstcMfs); 00257 static stc_mfs_intern_data_t* MfsLinGetInternDataPtr(volatile stc_mfsn_lin_t* pstcMfs); 00258 00259 /******************************************************************************/ 00260 /* Local variable definitions ('static') */ 00261 /******************************************************************************/ 00262 00263 /******************************************************************************/ 00264 /* Function implementation - global ('extern') and local ('static') */ 00265 /******************************************************************************/ 00266 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ 00267 (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ 00268 (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ 00269 (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ 00270 (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ 00271 (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ 00272 (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ 00273 (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 00274 00283 static void Mfs_InitIrq(en_mfs_instance_index_t enIndex, boolean_t bRxTx) 00284 { 00285 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) 00286 if (enIndex == MfsInstanceIndexMfs0) 00287 { 00288 if(bRxTx == FALSE) 00289 { 00290 /* MFS0/8 receive interrupt settings */ 00291 NVIC_ClearPendingIRQ(MFS0_8_RX_IRQn); 00292 NVIC_EnableIRQ(MFS0_8_RX_IRQn); 00293 NVIC_SetPriority(MFS0_8_RX_IRQn, PDL_IRQ_LEVEL_MFS0_8_RX); 00294 } 00295 else 00296 { 00297 /* MFS0/8 transmit interrupt settings */ 00298 NVIC_ClearPendingIRQ(MFS0_8_TX_IRQn); 00299 NVIC_EnableIRQ(MFS0_8_TX_IRQn); 00300 NVIC_SetPriority(MFS0_8_TX_IRQn, PDL_IRQ_LEVEL_MFS0_8_TX); 00301 } 00302 } 00303 #endif 00304 00305 #if (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) 00306 if (enIndex == MfsInstanceIndexMfs8) 00307 { 00308 if(bRxTx == FALSE) 00309 { 00310 /* MFS0/8 receive interrupt settings */ 00311 NVIC_ClearPendingIRQ(MFS0_8_RX_IRQn); 00312 NVIC_EnableIRQ(MFS0_8_RX_IRQn); 00313 NVIC_SetPriority(MFS0_8_RX_IRQn, PDL_IRQ_LEVEL_MFS0_8_RX); 00314 } 00315 else 00316 { 00317 /* MFS0/8 transmit interrupt settings */ 00318 NVIC_ClearPendingIRQ(MFS0_8_TX_IRQn); 00319 NVIC_EnableIRQ(MFS0_8_TX_IRQn); 00320 NVIC_SetPriority(MFS0_8_TX_IRQn, PDL_IRQ_LEVEL_MFS0_8_TX); 00321 } 00322 } 00323 #endif 00324 00325 #if (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) 00326 if (enIndex == MfsInstanceIndexMfs1) 00327 { 00328 if(bRxTx == FALSE) 00329 { 00330 /* MFS1/9 receive interrupt settings */ 00331 NVIC_ClearPendingIRQ(MFS1_9_RX_IRQn); 00332 NVIC_EnableIRQ(MFS1_9_RX_IRQn); 00333 NVIC_SetPriority(MFS1_9_RX_IRQn, PDL_IRQ_LEVEL_MFS1_9_RX); 00334 } 00335 else 00336 { 00337 /* MFS1/9 transmit interrupt settings */ 00338 NVIC_ClearPendingIRQ(MFS1_9_TX_IRQn); 00339 NVIC_EnableIRQ(MFS1_9_TX_IRQn); 00340 NVIC_SetPriority(MFS1_9_TX_IRQn, PDL_IRQ_LEVEL_MFS1_9_TX); 00341 } 00342 } 00343 #endif 00344 00345 #if (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) 00346 if (enIndex == MfsInstanceIndexMfs9) 00347 { 00348 if(bRxTx == FALSE) 00349 { 00350 /* MFS1/9 receive interrupt settings */ 00351 NVIC_ClearPendingIRQ(MFS1_9_RX_IRQn); 00352 NVIC_EnableIRQ(MFS1_9_RX_IRQn); 00353 NVIC_SetPriority(MFS1_9_RX_IRQn, PDL_IRQ_LEVEL_MFS1_9_RX); 00354 } 00355 else 00356 { 00357 /* MFS1/9 transmit interrupt settings */ 00358 NVIC_ClearPendingIRQ(MFS1_9_TX_IRQn); 00359 NVIC_EnableIRQ(MFS1_9_TX_IRQn); 00360 NVIC_SetPriority(MFS1_9_TX_IRQn, PDL_IRQ_LEVEL_MFS1_9_TX); 00361 } 00362 } 00363 #endif 00364 00365 #if (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) 00366 if (enIndex == MfsInstanceIndexMfs2) 00367 { 00368 if(bRxTx == FALSE) 00369 { 00370 /* MFS2/10 receive interrupt settings */ 00371 NVIC_ClearPendingIRQ(MFS2_10_RX_IRQn); 00372 NVIC_EnableIRQ(MFS2_10_RX_IRQn); 00373 NVIC_SetPriority(MFS2_10_RX_IRQn, PDL_IRQ_LEVEL_MFS2_10_RX); 00374 } 00375 else 00376 { 00377 /* MFS2/10 transmit interrupt settings */ 00378 NVIC_ClearPendingIRQ(MFS2_10_TX_IRQn); 00379 NVIC_EnableIRQ(MFS2_10_TX_IRQn); 00380 NVIC_SetPriority(MFS2_10_TX_IRQn, PDL_IRQ_LEVEL_MFS2_10_TX); 00381 } 00382 } 00383 #endif 00384 00385 #if (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) 00386 if (enIndex == MfsInstanceIndexMfs10) 00387 { 00388 if(bRxTx == FALSE) 00389 { 00390 /* MFS2/10 receive interrupt settings */ 00391 NVIC_ClearPendingIRQ(MFS2_10_RX_IRQn); 00392 NVIC_EnableIRQ(MFS2_10_RX_IRQn); 00393 NVIC_SetPriority(MFS2_10_RX_IRQn, PDL_IRQ_LEVEL_MFS2_10_RX); 00394 } 00395 else 00396 { 00397 /* MFS2/10 transmit interrupt settings */ 00398 NVIC_ClearPendingIRQ(MFS2_10_TX_IRQn); 00399 NVIC_EnableIRQ(MFS2_10_TX_IRQn); 00400 NVIC_SetPriority(MFS2_10_TX_IRQn, PDL_IRQ_LEVEL_MFS2_10_TX); 00401 } 00402 } 00403 #endif 00404 00405 #if (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) 00406 if (enIndex == MfsInstanceIndexMfs3) 00407 { 00408 if(bRxTx == FALSE) 00409 { 00410 /* MFS3/11 receive interrupt settings */ 00411 NVIC_ClearPendingIRQ(MFS3_11_RX_IRQn); 00412 NVIC_EnableIRQ(MFS3_11_RX_IRQn); 00413 NVIC_SetPriority(MFS3_11_RX_IRQn, PDL_IRQ_LEVEL_MFS3_11_RX); 00414 } 00415 else 00416 { 00417 /* MFS3/11 transmit interrupt settings */ 00418 NVIC_ClearPendingIRQ(MFS3_11_TX_IRQn); 00419 NVIC_EnableIRQ(MFS3_11_TX_IRQn); 00420 NVIC_SetPriority(MFS3_11_TX_IRQn, PDL_IRQ_LEVEL_MFS3_11_TX); 00421 } 00422 } 00423 #endif 00424 00425 #if (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) 00426 if (enIndex == MfsInstanceIndexMfs11) 00427 { 00428 if(bRxTx == FALSE) 00429 { 00430 /* MFS3/11 receive interrupt settings */ 00431 NVIC_ClearPendingIRQ(MFS3_11_RX_IRQn); 00432 NVIC_EnableIRQ(MFS3_11_RX_IRQn); 00433 NVIC_SetPriority(MFS3_11_RX_IRQn, PDL_IRQ_LEVEL_MFS3_11_RX); 00434 } 00435 else 00436 { 00437 /* MFS3/11 transmit interrupt settings */ 00438 NVIC_ClearPendingIRQ(MFS3_11_TX_IRQn); 00439 NVIC_EnableIRQ(MFS3_11_TX_IRQn); 00440 NVIC_SetPriority(MFS3_11_TX_IRQn, PDL_IRQ_LEVEL_MFS3_11_TX); 00441 } 00442 } 00443 #endif 00444 00445 #if (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) 00446 if (enIndex == MfsInstanceIndexMfs4) 00447 { 00448 if(bRxTx == FALSE) 00449 { 00450 /* MFS4/12 receive interrupt settings */ 00451 NVIC_ClearPendingIRQ(MFS4_12_RX_IRQn); 00452 NVIC_EnableIRQ(MFS4_12_RX_IRQn); 00453 NVIC_SetPriority(MFS4_12_RX_IRQn, PDL_IRQ_LEVEL_MFS4_12_RX); 00454 } 00455 else 00456 { 00457 /* MFS4/12 transmit interrupt settings */ 00458 NVIC_ClearPendingIRQ(MFS4_12_TX_IRQn); 00459 NVIC_EnableIRQ(MFS4_12_TX_IRQn); 00460 NVIC_SetPriority(MFS4_12_TX_IRQn, PDL_IRQ_LEVEL_MFS4_12_TX); 00461 } 00462 } 00463 #endif 00464 00465 #if (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) 00466 if (enIndex == MfsInstanceIndexMfs12) 00467 { 00468 if(bRxTx == FALSE) 00469 { 00470 /* MFS4/12 receive interrupt settings */ 00471 NVIC_ClearPendingIRQ(MFS4_12_RX_IRQn); 00472 NVIC_EnableIRQ(MFS4_12_RX_IRQn); 00473 NVIC_SetPriority(MFS4_12_RX_IRQn, PDL_IRQ_LEVEL_MFS4_12_RX); 00474 } 00475 else 00476 { 00477 /* MFS4/12 transmit interrupt settings */ 00478 NVIC_ClearPendingIRQ(MFS4_12_TX_IRQn); 00479 NVIC_EnableIRQ(MFS4_12_TX_IRQn); 00480 NVIC_SetPriority(MFS4_12_TX_IRQn, PDL_IRQ_LEVEL_MFS4_12_TX); 00481 } 00482 } 00483 #endif 00484 00485 #if (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) 00486 if (enIndex == MfsInstanceIndexMfs5) 00487 { 00488 if(bRxTx == FALSE) 00489 { 00490 /* MFS5/13 receive interrupt settings */ 00491 NVIC_ClearPendingIRQ(MFS5_13_RX_IRQn); 00492 NVIC_EnableIRQ(MFS5_13_RX_IRQn); 00493 NVIC_SetPriority(MFS5_13_RX_IRQn, PDL_IRQ_LEVEL_MFS5_13_RX); 00494 } 00495 else 00496 { 00497 /* MFS5/13 transmit interrupt settings */ 00498 NVIC_ClearPendingIRQ(MFS5_13_TX_IRQn); 00499 NVIC_EnableIRQ(MFS5_13_TX_IRQn); 00500 NVIC_SetPriority(MFS5_13_TX_IRQn, PDL_IRQ_LEVEL_MFS5_13_TX); 00501 } 00502 } 00503 #endif 00504 00505 #if (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) 00506 if (enIndex == MfsInstanceIndexMfs13) 00507 { 00508 if(bRxTx == FALSE) 00509 { 00510 /* MFS5/13 receive interrupt settings */ 00511 NVIC_ClearPendingIRQ(MFS5_13_RX_IRQn); 00512 NVIC_EnableIRQ(MFS5_13_RX_IRQn); 00513 NVIC_SetPriority(MFS5_13_RX_IRQn, PDL_IRQ_LEVEL_MFS5_13_RX); 00514 } 00515 else 00516 { 00517 /* MFS5/13 transmit interrupt settings */ 00518 NVIC_ClearPendingIRQ(MFS5_13_TX_IRQn); 00519 NVIC_EnableIRQ(MFS5_13_TX_IRQn); 00520 NVIC_SetPriority(MFS5_13_TX_IRQn, PDL_IRQ_LEVEL_MFS5_13_TX); 00521 } 00522 } 00523 #endif 00524 00525 #if (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) 00526 if (enIndex == MfsInstanceIndexMfs6) 00527 { 00528 if(bRxTx == FALSE) 00529 { 00530 /* MFS6/14 receive interrupt settings */ 00531 NVIC_ClearPendingIRQ(MFS6_14_RX_DMA0_IRQn); 00532 NVIC_EnableIRQ(MFS6_14_RX_DMA0_IRQn); 00533 NVIC_SetPriority(MFS6_14_RX_DMA0_IRQn, PDL_IRQ_LEVEL_MFS6_14_RX_DMA0); 00534 } 00535 else 00536 { 00537 /* MFS6/14 transmit interrupt settings */ 00538 NVIC_ClearPendingIRQ(MFS6_14_TX_DMA1_IRQn); 00539 NVIC_EnableIRQ(MFS6_14_TX_DMA1_IRQn); 00540 NVIC_SetPriority(MFS6_14_TX_DMA1_IRQn, PDL_IRQ_LEVEL_MFS6_14_TX_DMA1); 00541 } 00542 } 00543 #endif 00544 00545 #if (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) 00546 if (enIndex == MfsInstanceIndexMfs14) 00547 { 00548 if(bRxTx == FALSE) 00549 { 00550 /* MFS6/14 receive interrupt settings */ 00551 NVIC_ClearPendingIRQ(MFS6_14_RX_DMA0_IRQn); 00552 NVIC_EnableIRQ(MFS6_14_RX_DMA0_IRQn); 00553 NVIC_SetPriority(MFS6_14_RX_DMA0_IRQn, PDL_IRQ_LEVEL_MFS6_14_RX_DMA0); 00554 } 00555 else 00556 { 00557 /* MFS6/14 transmit interrupt settings */ 00558 NVIC_ClearPendingIRQ(MFS6_14_TX_DMA1_IRQn); 00559 NVIC_EnableIRQ(MFS6_14_TX_DMA1_IRQn); 00560 NVIC_SetPriority(MFS6_14_TX_DMA1_IRQn, PDL_IRQ_LEVEL_MFS6_14_TX_DMA1); 00561 } 00562 } 00563 #endif 00564 00565 #if (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) 00566 if (enIndex == MfsInstanceIndexMfs7) 00567 { 00568 if(bRxTx == FALSE) 00569 { 00570 /* MFS7/15 receive interrupt settings */ 00571 NVIC_ClearPendingIRQ(MFS7_15_RX_DMA2_IRQn); 00572 NVIC_EnableIRQ(MFS7_15_RX_DMA2_IRQn); 00573 NVIC_SetPriority(MFS7_15_RX_DMA2_IRQn, PDL_IRQ_LEVEL_MFS7_15_RX_DMA2); 00574 } 00575 else 00576 { 00577 /* MFS7/15 transmit interrupt settings */ 00578 NVIC_ClearPendingIRQ(MFS7_15_TX_DMA3_IRQn); 00579 NVIC_EnableIRQ(MFS7_15_TX_DMA3_IRQn); 00580 NVIC_SetPriority(MFS7_15_TX_DMA3_IRQn, PDL_IRQ_LEVEL_MFS7_15_TX_DMA3); 00581 } 00582 } 00583 #endif 00584 00585 #if (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 00586 if (enIndex == MfsInstanceIndexMfs15) 00587 { 00588 if(bRxTx == FALSE) 00589 { 00590 /* MFS7/15 receive interrupt settings */ 00591 NVIC_ClearPendingIRQ(MFS7_15_RX_DMA2_IRQn); 00592 NVIC_EnableIRQ(MFS7_15_RX_DMA2_IRQn); 00593 NVIC_SetPriority(MFS7_15_RX_DMA2_IRQn, PDL_IRQ_LEVEL_MFS7_15_RX_DMA2); 00594 } 00595 else 00596 { 00597 /* MFS7/15 transmit interrupt settings */ 00598 NVIC_ClearPendingIRQ(MFS7_15_TX_DMA3_IRQn); 00599 NVIC_EnableIRQ(MFS7_15_TX_DMA3_IRQn); 00600 NVIC_SetPriority(MFS7_15_TX_DMA3_IRQn, PDL_IRQ_LEVEL_MFS7_15_TX_DMA3); 00601 } 00602 } 00603 #endif 00604 00605 } /* Mfs_InitTxIrq */ 00606 00615 static void Mfs_DeInitIrq(en_mfs_instance_index_t enIndex, boolean_t bRxTx) 00616 { 00617 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) 00618 if (enIndex == MfsInstanceIndexMfs0) 00619 { 00620 if(bRxTx == FALSE) 00621 { 00622 /* MFS0/8 receive interrupt settings */ 00623 NVIC_ClearPendingIRQ(MFS0_8_RX_IRQn); 00624 NVIC_DisableIRQ(MFS0_8_RX_IRQn); 00625 NVIC_SetPriority(MFS0_8_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00626 } 00627 else 00628 { 00629 /* MFS0/8 tranfer interrupt settings */ 00630 NVIC_ClearPendingIRQ(MFS0_8_TX_IRQn); 00631 NVIC_DisableIRQ(MFS0_8_TX_IRQn); 00632 NVIC_SetPriority(MFS0_8_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00633 } 00634 00635 } 00636 #endif 00637 00638 #if (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) 00639 if (enIndex == MfsInstanceIndexMfs8) 00640 { 00641 if(bRxTx == FALSE) 00642 { 00643 /* MFS0/8 receive interrupt settings */ 00644 NVIC_ClearPendingIRQ(MFS0_8_RX_IRQn); 00645 NVIC_DisableIRQ(MFS0_8_RX_IRQn); 00646 NVIC_SetPriority(MFS0_8_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00647 } 00648 else 00649 { 00650 /* MFS0/8 tranfer interrupt settings */ 00651 NVIC_ClearPendingIRQ(MFS0_8_TX_IRQn); 00652 NVIC_DisableIRQ(MFS0_8_TX_IRQn); 00653 NVIC_SetPriority(MFS0_8_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00654 } 00655 00656 } 00657 #endif 00658 00659 #if (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) 00660 if (enIndex == MfsInstanceIndexMfs1) 00661 { 00662 if(bRxTx == FALSE) 00663 { 00664 /* MFS1/9 receive interrupt settings */ 00665 NVIC_ClearPendingIRQ(MFS1_9_RX_IRQn); 00666 NVIC_DisableIRQ(MFS1_9_RX_IRQn); 00667 NVIC_SetPriority(MFS1_9_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00668 } 00669 else 00670 { 00671 /* MFS1/9 transfer interrupt settings */ 00672 NVIC_ClearPendingIRQ(MFS1_9_TX_IRQn); 00673 NVIC_DisableIRQ(MFS1_9_TX_IRQn); 00674 NVIC_SetPriority(MFS1_9_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00675 } 00676 } 00677 #endif 00678 00679 #if (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) 00680 if (enIndex == MfsInstanceIndexMfs9) 00681 { 00682 if(bRxTx == FALSE) 00683 { 00684 /* MFS1/9 receive interrupt settings */ 00685 NVIC_ClearPendingIRQ(MFS1_9_RX_IRQn); 00686 NVIC_DisableIRQ(MFS1_9_RX_IRQn); 00687 NVIC_SetPriority(MFS1_9_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00688 } 00689 else 00690 { 00691 /* MFS1/9 transfer interrupt settings */ 00692 NVIC_ClearPendingIRQ(MFS1_9_TX_IRQn); 00693 NVIC_DisableIRQ(MFS1_9_TX_IRQn); 00694 NVIC_SetPriority(MFS1_9_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00695 } 00696 } 00697 #endif 00698 00699 #if (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) 00700 if (enIndex == MfsInstanceIndexMfs2) 00701 { 00702 if(bRxTx == FALSE) 00703 { 00704 /* MFS2/10 receive interrupt settings */ 00705 NVIC_ClearPendingIRQ(MFS2_10_RX_IRQn); 00706 NVIC_DisableIRQ(MFS2_10_RX_IRQn); 00707 NVIC_SetPriority(MFS2_10_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00708 } 00709 else 00710 { 00711 /* MFS2/10 transfer interrupt settings */ 00712 NVIC_ClearPendingIRQ(MFS2_10_TX_IRQn); 00713 NVIC_DisableIRQ(MFS2_10_TX_IRQn); 00714 NVIC_SetPriority(MFS2_10_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00715 } 00716 } 00717 #endif 00718 00719 #if (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) 00720 if (enIndex == MfsInstanceIndexMfs10) 00721 { 00722 if(bRxTx == FALSE) 00723 { 00724 /* MFS2/10 receive interrupt settings */ 00725 NVIC_ClearPendingIRQ(MFS2_10_RX_IRQn); 00726 NVIC_DisableIRQ(MFS2_10_RX_IRQn); 00727 NVIC_SetPriority(MFS2_10_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00728 } 00729 else 00730 { 00731 /* MFS2/10 transfer interrupt settings */ 00732 NVIC_ClearPendingIRQ(MFS2_10_TX_IRQn); 00733 NVIC_DisableIRQ(MFS2_10_TX_IRQn); 00734 NVIC_SetPriority(MFS2_10_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00735 } 00736 } 00737 #endif 00738 00739 #if (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) 00740 if (enIndex == MfsInstanceIndexMfs3) 00741 { 00742 if(bRxTx == FALSE) 00743 { 00744 /* MFS3/11 receive interrupt settings */ 00745 NVIC_ClearPendingIRQ(MFS3_11_RX_IRQn); 00746 NVIC_DisableIRQ(MFS3_11_RX_IRQn); 00747 NVIC_SetPriority(MFS3_11_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00748 } 00749 else 00750 { 00751 /* MFS3/11 transfer interrupt settings */ 00752 NVIC_ClearPendingIRQ(MFS3_11_TX_IRQn); 00753 NVIC_DisableIRQ(MFS3_11_TX_IRQn); 00754 NVIC_SetPriority(MFS3_11_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00755 } 00756 } 00757 #endif 00758 00759 #if (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) 00760 if (enIndex == MfsInstanceIndexMfs11) 00761 { 00762 if(bRxTx == FALSE) 00763 { 00764 /* MFS3/11 receive interrupt settings */ 00765 NVIC_ClearPendingIRQ(MFS3_11_RX_IRQn); 00766 NVIC_DisableIRQ(MFS3_11_RX_IRQn); 00767 NVIC_SetPriority(MFS3_11_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00768 } 00769 else 00770 { 00771 /* MFS3/11 transfer interrupt settings */ 00772 NVIC_ClearPendingIRQ(MFS3_11_TX_IRQn); 00773 NVIC_DisableIRQ(MFS3_11_TX_IRQn); 00774 NVIC_SetPriority(MFS3_11_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00775 } 00776 } 00777 #endif 00778 00779 #if (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) 00780 if (enIndex == MfsInstanceIndexMfs4) 00781 { 00782 if(bRxTx == FALSE) 00783 { 00784 /* MFS4/12 receive interrupt settings */ 00785 NVIC_ClearPendingIRQ(MFS4_12_RX_IRQn); 00786 NVIC_DisableIRQ(MFS4_12_RX_IRQn); 00787 NVIC_SetPriority(MFS4_12_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00788 } 00789 else 00790 { 00791 /* MFS4/12 transfer interrupt settings */ 00792 NVIC_ClearPendingIRQ(MFS4_12_TX_IRQn); 00793 NVIC_DisableIRQ(MFS4_12_TX_IRQn); 00794 NVIC_SetPriority(MFS4_12_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00795 } 00796 00797 } 00798 #endif 00799 00800 #if (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) 00801 if (enIndex == MfsInstanceIndexMfs12) 00802 { 00803 if(bRxTx == FALSE) 00804 { 00805 /* MFS4/12 receive interrupt settings */ 00806 NVIC_ClearPendingIRQ(MFS4_12_RX_IRQn); 00807 NVIC_DisableIRQ(MFS4_12_RX_IRQn); 00808 NVIC_SetPriority(MFS4_12_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00809 } 00810 else 00811 { 00812 /* MFS4/12 transfer interrupt settings */ 00813 NVIC_ClearPendingIRQ(MFS4_12_TX_IRQn); 00814 NVIC_DisableIRQ(MFS4_12_TX_IRQn); 00815 NVIC_SetPriority(MFS4_12_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00816 } 00817 00818 } 00819 #endif 00820 00821 #if (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) 00822 if (enIndex == MfsInstanceIndexMfs5) 00823 { 00824 if(bRxTx == FALSE) 00825 { 00826 /* MFS5/13 receive interrupt settings */ 00827 NVIC_ClearPendingIRQ(MFS5_13_RX_IRQn); 00828 NVIC_DisableIRQ(MFS5_13_RX_IRQn); 00829 NVIC_SetPriority(MFS5_13_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00830 } 00831 else 00832 { 00833 /* MFS5/13 transfer interrupt settings */ 00834 NVIC_ClearPendingIRQ(MFS5_13_TX_IRQn); 00835 NVIC_DisableIRQ(MFS5_13_TX_IRQn); 00836 NVIC_SetPriority(MFS5_13_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00837 } 00838 } 00839 #endif 00840 00841 #if (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) 00842 if (enIndex == MfsInstanceIndexMfs13) 00843 { 00844 if(bRxTx == FALSE) 00845 { 00846 /* MFS5/13 receive interrupt settings */ 00847 NVIC_ClearPendingIRQ(MFS5_13_RX_IRQn); 00848 NVIC_DisableIRQ(MFS5_13_RX_IRQn); 00849 NVIC_SetPriority(MFS5_13_RX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00850 } 00851 else 00852 { 00853 /* MFS5/13 transfer interrupt settings */ 00854 NVIC_ClearPendingIRQ(MFS5_13_TX_IRQn); 00855 NVIC_DisableIRQ(MFS5_13_TX_IRQn); 00856 NVIC_SetPriority(MFS5_13_TX_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00857 } 00858 } 00859 #endif 00860 00861 #if (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) 00862 if (enIndex == MfsInstanceIndexMfs6) 00863 { 00864 if(bRxTx == FALSE) 00865 { 00866 /* MFS6/14 receive interrupt settings */ 00867 NVIC_ClearPendingIRQ(MFS6_14_RX_DMA0_IRQn); 00868 NVIC_DisableIRQ(MFS6_14_RX_DMA0_IRQn); 00869 NVIC_SetPriority(MFS6_14_RX_DMA0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00870 } 00871 else 00872 { 00873 /* MFS6/14 transfer interrupt settings */ 00874 NVIC_ClearPendingIRQ(MFS6_14_TX_DMA1_IRQn); 00875 NVIC_DisableIRQ(MFS6_14_TX_DMA1_IRQn); 00876 NVIC_SetPriority(MFS6_14_TX_DMA1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00877 } 00878 } 00879 #endif 00880 00881 #if (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) 00882 if(enIndex == MfsInstanceIndexMfs14) 00883 { 00884 if(bRxTx == FALSE) 00885 { 00886 /* MFS6/14 receive interrupt settings */ 00887 NVIC_ClearPendingIRQ(MFS6_14_RX_DMA0_IRQn); 00888 NVIC_DisableIRQ(MFS6_14_RX_DMA0_IRQn); 00889 NVIC_SetPriority(MFS6_14_RX_DMA0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00890 } 00891 else 00892 { 00893 /* MFS6/14 transfer interrupt settings */ 00894 NVIC_ClearPendingIRQ(MFS6_14_TX_DMA1_IRQn); 00895 NVIC_DisableIRQ(MFS6_14_TX_DMA1_IRQn); 00896 NVIC_SetPriority(MFS6_14_TX_DMA1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00897 } 00898 } 00899 #endif 00900 00901 #if (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) 00902 if (enIndex == MfsInstanceIndexMfs7) 00903 { 00904 if(bRxTx == FALSE) 00905 { 00906 /* MFS7/15 receive interrupt settings */ 00907 NVIC_ClearPendingIRQ(MFS7_15_RX_DMA2_IRQn); 00908 NVIC_DisableIRQ(MFS7_15_RX_DMA2_IRQn); 00909 NVIC_SetPriority(MFS7_15_RX_DMA2_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00910 } 00911 else 00912 { 00913 /* MFS7/15 transfer interrupt settings */ 00914 NVIC_ClearPendingIRQ(MFS7_15_TX_DMA3_IRQn); 00915 NVIC_DisableIRQ(MFS7_15_TX_DMA3_IRQn); 00916 NVIC_SetPriority(MFS7_15_TX_DMA3_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00917 } 00918 } 00919 #endif 00920 00921 #if (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 00922 if (enIndex == MfsInstanceIndexMfs15) 00923 { 00924 if(bRxTx == FALSE) 00925 { 00926 /* MFS7/15 receive interrupt settings */ 00927 NVIC_ClearPendingIRQ(MFS7_15_RX_DMA2_IRQn); 00928 NVIC_DisableIRQ(MFS7_15_RX_DMA2_IRQn); 00929 NVIC_SetPriority(MFS7_15_RX_DMA2_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00930 } 00931 else 00932 { 00933 /* MFS7/15 transfer interrupt settings */ 00934 NVIC_ClearPendingIRQ(MFS7_15_TX_DMA3_IRQn); 00935 NVIC_DisableIRQ(MFS7_15_TX_DMA3_IRQn); 00936 NVIC_SetPriority(MFS7_15_TX_DMA3_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00937 } 00938 } 00939 #endif 00940 00941 } /* Mfs_DeInitIrq */ 00942 00943 #endif 00944 00945 /****************************************************************************** 00946 * UART driver functions 00947 ******************************************************************************/ 00948 00958 static stc_mfs_intern_data_t* MfsUartGetInternDataPtr(volatile stc_mfsn_uart_t* pstcUart) 00959 { 00960 stc_mfs_intern_data_t* pstcInternDataPtr = NULL; 00961 uint32_t u32Instance; 00962 00963 if (NULL != pstcUart) 00964 { 00965 for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) 00966 { 00967 if (pstcUart == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcUartInstance) 00968 { 00969 pstcInternDataPtr = &m_astcMfsInstanceDataLut[u32Instance].stcInternData; 00970 break; 00971 } 00972 } 00973 00974 } 00975 00976 return (pstcInternDataPtr); 00977 } /* MfsGetInternDataPtr */ 00978 00979 00980 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ 00981 (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ 00982 (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ 00983 (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ 00984 (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ 00985 (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ 00986 (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ 00987 (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 00988 00997 static en_mfs_instance_index_t MfsUartGetInstanceIndex(volatile stc_mfsn_uart_t* pstcUart) 00998 { 00999 en_mfs_instance_index_t enInstanceIndex = MfsInstanceIndexUnknown; 01000 uint32_t u32Instance; 01001 01002 if (NULL != pstcUart) 01003 { 01004 for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) 01005 { 01006 if (pstcUart == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcUartInstance) 01007 { 01008 enInstanceIndex = m_astcMfsInstanceDataLut[u32Instance].stcInternData.enIndex; 01009 break; 01010 } 01011 } 01012 01013 } 01014 01015 return (enInstanceIndex); 01016 } /* MfsUartGetInstanceIndex */ 01017 01018 01029 void MfsUartIrqHandlerRx( volatile stc_mfsn_uart_t* pstcUart, 01030 stc_mfs_intern_data_t* pstcMfsInternData) 01031 { 01032 if ((NULL != pstcUart) && (NULL != pstcMfsInternData)) 01033 { 01034 if (NULL != pstcMfsInternData->stcUartInternIntCb.pfnRxIntCb) 01035 { 01036 pstcMfsInternData->stcUartInternIntCb.pfnRxIntCb(); 01037 } 01038 } 01039 } /* MfsIrqHandlerRx */ 01040 01051 void MfsUartIrqHandlerTx( volatile stc_mfsn_uart_t* pstcUart, 01052 stc_mfs_intern_data_t* pstcMfsInternData) 01053 { 01054 if ((NULL != pstcUart) && (NULL != pstcMfsInternData)) 01055 { 01056 if(pstcUart->SSR_f.TDRE == 1) 01057 { 01058 if (NULL != pstcMfsInternData->stcUartInternIntCb.pfnTxIntCb) 01059 { 01060 pstcMfsInternData->stcUartInternIntCb.pfnTxIntCb(); 01061 } 01062 } 01063 01064 if(pstcUart->SSR_f.TBI == 1) 01065 { 01066 if (NULL != pstcMfsInternData->stcUartInternIntCb.pfnTxIdleCb) 01067 { 01068 pstcMfsInternData->stcUartInternIntCb.pfnTxIdleCb(); 01069 } 01070 } 01071 01072 if(pstcUart->FCR1_f.FDRQ == 1) 01073 { 01074 if (NULL != pstcMfsInternData->stcUartInternIntCb.pfnTxFifoIntCb) 01075 { 01076 pstcMfsInternData->stcUartInternIntCb.pfnTxFifoIntCb(); 01077 } 01078 01079 pstcUart->FCR1_f.FDRQ = 0; 01080 } 01081 } 01082 } /* MfsIrqHandlerTx */ 01083 01104 en_result_t Mfs_Uart_EnableInt(volatile stc_mfsn_uart_t* pstcUart, 01105 stc_uart_int_sel_t* pstcInt, 01106 stc_uart_int_cb_t* pstcIntCb) 01107 { 01108 stc_mfs_intern_data_t* pstcMfsInternData; 01109 en_mfs_instance_index_t enIndex; 01110 01111 /* Check for valid pointer and get pointer to internal data struct ... */ 01112 pstcMfsInternData = MfsUartGetInternDataPtr(pstcUart); 01113 enIndex = MfsUartGetInstanceIndex(pstcUart); 01114 01115 if ((NULL == pstcMfsInternData) || 01116 (NULL == pstcInt) || 01117 (NULL == pstcIntCb) || 01118 (MfsInstanceIndexUnknown == enIndex)) 01119 { 01120 return (ErrorInvalidParameter); 01121 } 01122 01123 if(pstcInt->bRxInt == TRUE) 01124 { 01125 pstcMfsInternData->stcUartInternIntCb.pfnRxIntCb = pstcIntCb->pfnRxIntCb; 01126 pstcUart->SCR_f.RIE = 1; 01127 } 01128 01129 if(pstcInt->bTxInt == TRUE) 01130 { 01131 pstcMfsInternData->stcUartInternIntCb.pfnTxIntCb = pstcIntCb->pfnTxIntCb; 01132 pstcUart->SCR_f.TIE = 1; 01133 } 01134 01135 if(pstcInt->bTxIdle == TRUE) 01136 { 01137 pstcMfsInternData->stcUartInternIntCb.pfnTxIdleCb = pstcIntCb->pfnTxIdleCb; 01138 pstcUart->SCR_f.TBIE = 1; 01139 } 01140 01141 if(pstcInt->bTxFifoInt == TRUE) 01142 { 01143 pstcMfsInternData->stcUartInternIntCb.pfnTxFifoIntCb = pstcIntCb->pfnTxFifoIntCb; 01144 pstcUart->FCR1_f.FTIE = 1; 01145 } 01146 01147 if(pstcInt->bRxInt == TRUE) 01148 { 01149 Mfs_InitIrq(enIndex, FALSE); 01150 } 01151 01152 if((pstcInt->bTxInt == TRUE) || (pstcInt->bTxIdle == TRUE) || (pstcInt->bTxFifoInt == TRUE)) 01153 { 01154 Mfs_InitIrq(enIndex, TRUE); 01155 } 01156 01157 return Ok; 01158 } 01159 01177 en_result_t Mfs_Uart_DisableInt(volatile stc_mfsn_uart_t* pstcUart, 01178 stc_uart_int_sel_t* pstcInt) 01179 { 01180 stc_mfs_intern_data_t* pstcMfsInternData; 01181 en_mfs_instance_index_t enIndex; 01182 uint8_t u8Ch; 01183 01184 /* Check for valid pointer and get pointer to internal data struct ... */ 01185 pstcMfsInternData = MfsUartGetInternDataPtr(pstcUart); 01186 enIndex = MfsUartGetInstanceIndex(pstcUart); 01187 01188 if ((NULL == pstcMfsInternData) || 01189 (NULL == pstcInt) || 01190 (MfsInstanceIndexUnknown == enIndex)) 01191 { 01192 return (ErrorInvalidParameter); 01193 } 01194 01195 u8Ch = UartInstanceToIndex(pstcUart); 01196 01197 if(pstcInt->bRxInt == TRUE) 01198 { 01199 pstcMfsInternData->stcUartInternIntCb.pfnRxIntCb = NULL; 01200 pstcUart->SCR_f.RIE = 0; 01201 } 01202 01203 if(pstcInt->bTxInt == TRUE) 01204 { 01205 pstcMfsInternData->stcUartInternIntCb.pfnTxIntCb = NULL; 01206 pstcUart->SCR_f.TIE = 0; 01207 } 01208 01209 if(pstcInt->bTxIdle == TRUE) 01210 { 01211 pstcMfsInternData->stcUartInternIntCb.pfnTxIdleCb = NULL; 01212 pstcUart->SCR_f.TBIE = 0; 01213 } 01214 01215 if(pstcInt->bTxFifoInt == TRUE) 01216 { 01217 pstcMfsInternData->stcUartInternIntCb.pfnTxFifoIntCb = NULL; 01218 pstcUart->FCR1_f.FTIE = 0; 01219 } 01220 01221 // Only when RX interrupts and DMA interrupt(share same IRQ with MFS ch.14, ch.15) 01222 // are all disabled, disable RX IRQ 01223 do 01224 { 01225 if(pstcUart->SCR_f.RIE == 1) 01226 { 01227 break; 01228 } 01229 01230 if(u8Ch == 14u) 01231 { 01232 if((FM0P_DMAC->DMACB0_f.CI == 1) || (FM0P_DMAC->DMACB0_f.EI == 1)) 01233 { 01234 break; 01235 } 01236 } 01237 01238 if(u8Ch == 15u) 01239 { 01240 if((FM0P_DMAC->DMACB2_f.CI == 1) || (FM0P_DMAC->DMACB2_f.EI == 1)) 01241 { 01242 break; 01243 } 01244 } 01245 01246 Mfs_DeInitIrq(enIndex, FALSE); 01247 01248 }while(0); 01249 01250 // Only when TX interrupts and DMA interrupt(share same IRQ with MFS ch.14, ch.15) 01251 // are all disabled, disable TX IRQ 01252 do 01253 { 01254 if(pstcUart->SCR_f.TIE == 1) 01255 { 01256 break; 01257 } 01258 01259 if(pstcUart->SCR_f.TBIE == 1) 01260 { 01261 break; 01262 } 01263 01264 if(pstcUart->FCR1_f.FTIE == 1) 01265 { 01266 break; 01267 } 01268 01269 if(u8Ch == 14u) 01270 { 01271 if((FM0P_DMAC->DMACB1_f.CI == 0) && (FM0P_DMAC->DMACB1_f.EI == 0)) 01272 { 01273 break; 01274 } 01275 } 01276 01277 if(u8Ch == 15u) 01278 { 01279 if((FM0P_DMAC->DMACB3_f.CI == 0) && (FM0P_DMAC->DMACB3_f.EI == 0)) 01280 { 01281 break; 01282 } 01283 } 01284 01285 Mfs_DeInitIrq(enIndex, TRUE); 01286 01287 }while(0); 01288 01289 return Ok; 01290 } 01291 01292 #endif 01293 01311 en_result_t Mfs_Uart_Init(volatile stc_mfsn_uart_t* pstcUart, 01312 const stc_mfs_uart_config_t* pstcConfig) 01313 { 01314 stc_mfs_intern_data_t* pstcMfsInternData; 01315 01316 /* Preset local register variables to zero */ 01317 stc_mfs_uart_smr_field_t stcSMR = { 0 }; 01318 stc_mfs_uart_scr_field_t stcSCR = { 0 }; 01319 stc_mfs_uart_escr_field_t stcESCR = { 0 }; 01320 01321 /* Check for valid pointer and get pointer to internal data struct ... */ 01322 pstcMfsInternData = MfsUartGetInternDataPtr(pstcUart); 01323 01324 /* Parameter check and get ptr to internal data struct */ 01325 if ((NULL == pstcMfsInternData) 01326 || (NULL == pstcConfig) 01327 ) 01328 { 01329 return (ErrorInvalidParameter); 01330 } 01331 01332 /* Set the MFS mode in the internal structure */ 01333 pstcMfsInternData->enMode = MfsUartMode; 01334 01335 /* Set UART mode */ 01336 switch (pstcConfig->enMode) 01337 { 01338 case UartNormal: 01339 stcSMR.MD = 0u; /* Normal mode */ 01340 break; 01341 case UartMulti: 01342 stcSMR.MD = 1u; /* Multi-processor mode */ 01343 break; 01344 default: 01345 return (ErrorInvalidParameter); 01346 } 01347 01348 /* Enable SOE */ 01349 stcSMR.SOE = TRUE; 01350 /* Set Parity */ 01351 switch(pstcConfig->enParity) 01352 { 01353 case UartParityNone: 01354 stcESCR.P = FALSE; /* Parity type selection (0-even/1-odd) */ 01355 stcESCR.PEN = FALSE; /* Parity disable */ 01356 break; 01357 case UartParityEven: 01358 stcESCR.P = FALSE; /* Parity type selection (0-even/1-odd) */ 01359 stcESCR.PEN = TRUE; /* Parity Enable */ 01360 break; 01361 case UartParityOdd: 01362 stcESCR.P = TRUE; /* Parity type selection (0-even/1-odd) */ 01363 stcESCR.PEN = TRUE; /* Parity Enable */ 01364 break; 01365 default: 01366 return (ErrorInvalidParameter); 01367 } 01368 /* Set Stop bit length */ 01369 switch (pstcConfig->enStopBit) 01370 { 01371 case UartOneStopBit: 01372 stcSMR.SBL = FALSE; 01373 stcESCR.ESBL = FALSE; 01374 break; 01375 case UartTwoStopBits: 01376 stcSMR.SBL = TRUE; 01377 stcESCR.ESBL = FALSE; 01378 break; 01379 case UartThreeStopBits: 01380 stcSMR.SBL = FALSE; 01381 stcESCR.ESBL = TRUE; 01382 break; 01383 case UartFourStopBits: 01384 stcSMR.SBL = TRUE; 01385 stcESCR.ESBL = TRUE; 01386 break; 01387 default: 01388 return (ErrorInvalidParameter); 01389 } 01390 /* Set Data bit length (5 - 9bits) */ 01391 switch(pstcConfig->enDataLength) 01392 { 01393 case UartFiveBits: 01394 stcESCR.L = UartFiveBits; 01395 break; 01396 case UartSixBits: 01397 stcESCR.L = UartSixBits; 01398 break; 01399 case UartSevenBits: 01400 stcESCR.L = UartSevenBits; 01401 break; 01402 case UartEightBits: 01403 stcESCR.L = UartEightBits; 01404 break; 01405 case UartNineBits: 01406 stcESCR.L = UartNineBits; 01407 break; 01408 default: 01409 return (ErrorInvalidParameter); 01410 } 01411 /* Set Bit direction (LSB/MSB) */ 01412 switch(pstcConfig->enBitDirection) 01413 { 01414 case UartDataLsbFirst: 01415 stcSMR.BDS = 0; 01416 break; 01417 case UartDataMsbFirst: 01418 stcSMR.BDS = 1; 01419 break; 01420 default: 01421 return ErrorInvalidParameter; 01422 } 01423 01424 /* HW Flow */ 01425 if (TRUE == pstcConfig->bHwFlow) 01426 { 01427 stcESCR.FLWEN = TRUE; 01428 } 01429 else 01430 { 01431 stcESCR.FLWEN = FALSE; 01432 } 01433 01434 /* Set Signal system (NRZ/Int-NRZ) */ 01435 if (TRUE == pstcConfig->bInvertData) 01436 { 01437 stcESCR.INV = TRUE; 01438 } 01439 else 01440 { 01441 stcESCR.INV = FALSE; 01442 } 01443 01444 /* Clear MFS by setting the Software Reset bit */ 01445 pstcUart->SCR_f.UPCL = TRUE; 01446 01447 /* Set Baudrate */ 01448 (void)Mfs_Uart_SetBaudRate(pstcUart, pstcConfig->u32BautRate); 01449 /* Set registers value */ 01450 pstcUart->SMR_f = stcSMR; 01451 pstcUart->SCR_f = stcSCR; 01452 pstcUart->ESCR_f = stcESCR; 01453 01454 if(pstcConfig->bEnableFifo == TRUE) 01455 { 01456 /* Reset FIFO */ 01457 pstcUart->FCR0_f.FCL1 = 1; 01458 pstcUart->FCR0_f.FCL2 = 1; 01459 /* Enable FIFO receive Idle detection */ 01460 pstcUart->FCR1_f.FRIIE = 1; 01461 /* Selection TX and RX FIFO */ 01462 switch(pstcConfig->stcFifoConfig.enFifoSel) 01463 { 01464 case MfsTxFifo1RxFifo2: 01465 pstcUart->FCR1_f.FSEL = 0; 01466 break; 01467 case MfsTxFifo2RxFifo1: 01468 pstcUart->FCR1_f.FSEL = 1; 01469 break; 01470 default: 01471 return (ErrorInvalidParameter); 01472 } 01473 /* Set FIFO count */ 01474 pstcUart->FBYTE1 = pstcConfig->stcFifoConfig.u8ByteCount1; 01475 pstcUart->FBYTE2 = pstcConfig->stcFifoConfig.u8ByteCount2; 01476 /* Enable FIFO */ 01477 pstcUart->FCR0_f.FE1 = 1; 01478 pstcUart->FCR0_f.FE2 = 1; 01479 } 01480 01481 return (Ok); 01482 } /* MFS_Uart_Init */ 01483 01499 en_result_t Mfs_Uart_DeInit(volatile stc_mfsn_uart_t* pstcUart) 01500 { 01501 en_result_t enResult; 01502 stc_mfs_intern_data_t* pstcMfsInternData; 01503 01504 /* Check for valid pointer and get pointer to internal data struct ... */ 01505 pstcMfsInternData = MfsUartGetInternDataPtr(pstcUart); 01506 /* ... and check */ 01507 if (NULL == pstcMfsInternData) 01508 { 01509 enResult = ErrorInvalidParameter; 01510 } 01511 else 01512 { 01513 pstcUart->SCR_f.TXE = FALSE; 01514 pstcUart->SCR_f.RXE = FALSE; 01515 01516 /* Baud Rate Generation Reload Reset */ 01517 pstcUart->BGR = 0u; 01518 01519 /* Serial Mode Register clear all bits (valid in any mode) */ 01520 pstcUart->SMR = 0u; 01521 01522 /* Reset Mfs receive and transmit bit to default */ 01523 /* and clear all error flags */ 01524 pstcUart->SCR = 0u; 01525 01526 /* Clear reception Errors */ 01527 pstcUart->SSR_f.REC = TRUE; 01528 01529 /* Reset all other used register to default value */ 01530 pstcUart->SSR = 0u; 01531 pstcUart->ESCR = 0u; 01532 pstcUart->FCR0 = 0u; 01533 pstcUart->FCR1 = 0u; 01534 01535 /* Clear MFS by setting the Software Reset bit */ 01536 pstcUart->SCR_f.UPCL = TRUE; 01537 01538 enResult = Ok; 01539 } 01540 01541 return (enResult); 01542 } /* Mfs_Uart_DeInit */ 01543 01560 en_result_t Mfs_Uart_SetBaudRate(volatile stc_mfsn_uart_t* pstcUart, 01561 uint32_t u32BaudRate) 01562 { 01563 uint32_t u32Pclk1; 01564 01565 if ((NULL == pstcUart) || (u32BaudRate < 4)) 01566 { 01567 return ErrorInvalidParameter; 01568 } 01569 01570 u32Pclk1 = __HCLK/(1ul << (APBC1_PSR_Val & 0x03u)); /* MFS is attached on APB1 bus */ 01571 01572 pstcUart->BGR_f.BGR = (u32Pclk1/u32BaudRate) - 1; 01573 01574 return Ok; 01575 } 01576 01592 en_result_t Mfs_Uart_EnableFunc(volatile stc_mfsn_uart_t* pstcUart, en_uart_func_t enFunc) 01593 { 01594 if (NULL == pstcUart) 01595 { 01596 return ErrorInvalidParameter; 01597 } 01598 01599 switch(enFunc) 01600 { 01601 case UartTx: 01602 pstcUart->SCR_f.TXE = 1; 01603 break; 01604 case UartRx: 01605 pstcUart->SCR_f.RXE = 1; 01606 break; 01607 default: 01608 return ErrorInvalidParameter; 01609 } 01610 01611 return Ok; 01612 } 01613 01629 en_result_t Mfs_Uart_DisableFunc(volatile stc_mfsn_uart_t* pstcUart, en_uart_func_t enFunc) 01630 { 01631 if (NULL == pstcUart) 01632 { 01633 return ErrorInvalidParameter; 01634 } 01635 01636 switch(enFunc) 01637 { 01638 case UartTx: 01639 pstcUart->SCR_f.TXE = 0; 01640 break; 01641 case UartRx: 01642 pstcUart->SCR_f.RXE = 0; 01643 break; 01644 default: 01645 return ErrorInvalidParameter; 01646 } 01647 01648 return Ok; 01649 } 01650 01680 boolean_t Mfs_Uart_GetStatus(volatile stc_mfsn_uart_t* pstcUart, 01681 en_uart_status_t enStatus) 01682 { 01683 boolean_t bResult = FALSE; 01684 01685 switch(enStatus) 01686 { 01687 case UartParityError: 01688 bResult = (pstcUart->SSR_f.PE == 1) ? TRUE : FALSE; 01689 break; 01690 case UartFrameError: 01691 bResult = (pstcUart->SSR_f.FRE == 1) ? TRUE : FALSE; 01692 break; 01693 case UartOverrunError: 01694 bResult = (pstcUart->SSR_f.ORE == 1) ? TRUE : FALSE; 01695 break; 01696 case UartRxFull: 01697 bResult = (pstcUart->SSR_f.RDRF == 1) ? TRUE : FALSE; 01698 break; 01699 case UartTxEmpty: 01700 bResult = (pstcUart->SSR_f.TDRE == 1) ? TRUE : FALSE; 01701 break; 01702 case UartTxIdle: 01703 bResult = (pstcUart->SSR_f.TBI == 1) ? TRUE : FALSE; 01704 break; 01705 case UartTxFifoRequest: 01706 bResult = (pstcUart->FCR1_f.FDRQ == 1) ? TRUE : FALSE; 01707 break; 01708 default: 01709 break; 01710 } 01711 01712 return bResult; 01713 } 01714 01737 en_result_t Mfs_Uart_ClrStatus(volatile stc_mfsn_uart_t* pstcUart, 01738 en_uart_status_t enStatus) 01739 { 01740 if (NULL == pstcUart) 01741 { 01742 return ErrorInvalidParameter; 01743 } 01744 01745 switch(enStatus) 01746 { 01747 case UartParityError: 01748 case UartFrameError: 01749 case UartOverrunError: 01750 pstcUart->SSR_f.REC = 1; 01751 break; 01752 case UartRxFull: 01753 case UartTxEmpty: 01754 case UartTxIdle: 01755 break; 01756 case UartTxFifoRequest: 01757 pstcUart->FCR1_f.FDRQ = 0; 01758 break; 01759 default: 01760 return ErrorInvalidParameter; 01761 } 01762 01763 return Ok; 01764 } 01765 01778 en_result_t Mfs_Uart_SendData(volatile stc_mfsn_uart_t* pstcUart, uint16_t u16Data) 01779 { 01780 if (NULL == pstcUart) 01781 { 01782 return ErrorInvalidParameter; 01783 } 01784 01785 pstcUart->TDR = u16Data; 01786 01787 return Ok; 01788 } 01789 01799 uint16_t Mfs_Uart_ReceiveData(volatile stc_mfsn_uart_t* pstcUart) 01800 { 01801 return (pstcUart->RDR); 01802 } 01803 01816 en_result_t Mfs_Uart_ResetFifo (volatile stc_mfsn_uart_t* pstcUart, 01817 en_mfs_fifo_t enFifo) 01818 { 01819 if (NULL == pstcUart) 01820 { 01821 return ErrorInvalidParameter; 01822 } 01823 01824 switch(enFifo) 01825 { 01826 case MfsFifo1: 01827 pstcUart->FCR0_f.FCL1 = 1; 01828 break; 01829 case MfsFifo2: 01830 pstcUart->FCR0_f.FCL2 = 1; 01831 break; 01832 default: 01833 return ErrorInvalidParameter; 01834 } 01835 01836 return Ok; 01837 } 01838 01852 en_result_t Mfs_Uart_SetFifoCount(volatile stc_mfsn_uart_t* pstcUart, 01853 en_mfs_fifo_t enFifo, 01854 uint8_t u8Count) 01855 { 01856 if (NULL == pstcUart) 01857 { 01858 return ErrorInvalidParameter; 01859 } 01860 01861 switch(enFifo) 01862 { 01863 case MfsFifo1: 01864 pstcUart->FBYTE1 = u8Count; 01865 break; 01866 case MfsFifo2: 01867 pstcUart->FBYTE2 = u8Count; 01868 break; 01869 default: 01870 return ErrorInvalidParameter; 01871 } 01872 01873 return Ok; 01874 } 01875 01890 uint8_t Mfs_Uart_GetFifoCount(volatile stc_mfsn_uart_t* pstcUart, 01891 en_mfs_fifo_t enFifo) 01892 { 01893 uint8_t u8FifoCnt = 0xFFu; 01894 01895 switch(enFifo) 01896 { 01897 case MfsFifo1: 01898 u8FifoCnt = pstcUart->FBYTE1; 01899 break; 01900 case MfsFifo2: 01901 u8FifoCnt = pstcUart->FBYTE2; 01902 break; 01903 default: 01904 break; 01905 } 01906 01907 return u8FifoCnt; 01908 } 01909 01910 /****************************************************************************** 01911 * CSIO driver functions 01912 ******************************************************************************/ 01913 01923 static stc_mfs_intern_data_t* MfsCsioGetInternDataPtr(volatile stc_mfsn_csio_t* pstcCsio) 01924 { 01925 stc_mfs_intern_data_t* pstcInternDataPtr = NULL; 01926 uint32_t u32Instance; 01927 01928 if (NULL != pstcCsio) 01929 { 01930 for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) 01931 { 01932 if (pstcCsio == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcCsioInstance) 01933 { 01934 pstcInternDataPtr = &m_astcMfsInstanceDataLut[u32Instance].stcInternData; 01935 break; 01936 } 01937 } 01938 01939 } 01940 01941 return (pstcInternDataPtr); 01942 } /* MfsGetInternDataPtr */ 01943 01944 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ 01945 (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ 01946 (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ 01947 (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ 01948 (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ 01949 (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ 01950 (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ 01951 (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 01952 01961 static en_mfs_instance_index_t MfsCsioGetInstanceIndex(volatile stc_mfsn_csio_t* pstcCsio) 01962 { 01963 en_mfs_instance_index_t enInstanceIndex = MfsInstanceIndexUnknown; 01964 uint32_t u32Instance; 01965 01966 if (NULL != pstcCsio) 01967 { 01968 for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) 01969 { 01970 if (pstcCsio == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcCsioInstance) 01971 { 01972 enInstanceIndex = m_astcMfsInstanceDataLut[u32Instance].stcInternData.enIndex; 01973 break; 01974 } 01975 } 01976 01977 } 01978 01979 return (enInstanceIndex); 01980 } /* MfsCsioGetInstanceIndex */ 01981 01992 void MfsCsioIrqHandlerRx( volatile stc_mfsn_csio_t* pstcCsio, 01993 stc_mfs_intern_data_t* pstcMfsInternData) 01994 { 01995 if ((NULL != pstcCsio) && (NULL != pstcMfsInternData)) 01996 { 01997 if (NULL != pstcMfsInternData->stcCsioInternIntCb.pfnRxIntCb) 01998 { 01999 pstcMfsInternData->stcCsioInternIntCb.pfnRxIntCb(); 02000 } 02001 } 02002 } /* MfsCsioIrqHandlerRx */ 02003 02014 void MfsCsioIrqHandlerTx( volatile stc_mfsn_csio_t* pstcCsio, 02015 stc_mfs_intern_data_t* pstcMfsInternData) 02016 { 02017 if ((NULL != pstcCsio) && (NULL != pstcMfsInternData)) 02018 { 02019 if(pstcCsio->SSR_f.TDRE == 1) 02020 { 02021 if (NULL != pstcMfsInternData->stcCsioInternIntCb.pfnTxIntCb) 02022 { 02023 pstcMfsInternData->stcCsioInternIntCb.pfnTxIntCb(); 02024 } 02025 } 02026 02027 if(pstcCsio->SSR_f.TBI == 1) 02028 { 02029 if (NULL != pstcMfsInternData->stcCsioInternIntCb.pfnTxIdleCb) 02030 { 02031 pstcMfsInternData->stcCsioInternIntCb.pfnTxIdleCb(); 02032 } 02033 } 02034 02035 if(pstcCsio->FCR1_f.FDRQ == 1) 02036 { 02037 if (NULL != pstcMfsInternData->stcCsioInternIntCb.pfnTxFifoIntCb) 02038 { 02039 pstcMfsInternData->stcCsioInternIntCb.pfnTxFifoIntCb(); 02040 } 02041 02042 pstcCsio->FCR1_f.FDRQ = 0; 02043 } 02044 02045 if(pstcCsio->SACSR_f.CSE == 1) 02046 { 02047 if (NULL != pstcMfsInternData->stcCsioInternIntCb.pfnCsErrIntCb) 02048 { 02049 pstcMfsInternData->stcCsioInternIntCb.pfnCsErrIntCb(); 02050 } 02051 02052 pstcCsio->SACSR_f.CSE = 0; 02053 } 02054 02055 } 02056 } /* MfsIrqHandlerTx */ 02057 02068 void MfsCsioIrqHandlerStatus( volatile stc_mfsn_csio_t* pstcCsio, 02069 stc_mfs_intern_data_t* pstcMfsInternData) 02070 { 02071 if ((NULL != pstcCsio) && (NULL != pstcMfsInternData)) 02072 { 02073 if(pstcCsio->SACSR_f.TINT == 1) 02074 { 02075 if (NULL != pstcMfsInternData->stcCsioInternIntCb.pfnSerialTimerIntCb) 02076 { 02077 pstcMfsInternData->stcCsioInternIntCb.pfnSerialTimerIntCb(); 02078 } 02079 02080 pstcCsio->SACSR_f.TINT = 0; 02081 } 02082 } 02083 } 02084 02105 en_result_t Mfs_Csio_EnableInt(volatile stc_mfsn_csio_t* pstcCsio, 02106 stc_csio_int_sel_t* pstcInt, 02107 stc_csio_int_cb_t* pstcIntCb) 02108 { 02109 stc_mfs_intern_data_t* pstcMfsInternData; 02110 en_mfs_instance_index_t enIndex; 02111 02112 /* Check for valid pointer and get pointer to internal data struct ... */ 02113 pstcMfsInternData = MfsCsioGetInternDataPtr(pstcCsio); 02114 enIndex = MfsCsioGetInstanceIndex(pstcCsio); 02115 02116 if ((NULL == pstcMfsInternData) || 02117 (NULL == pstcInt) || 02118 (NULL == pstcIntCb) || 02119 (MfsInstanceIndexUnknown == enIndex)) 02120 { 02121 return (ErrorInvalidParameter); 02122 } 02123 02124 if(pstcInt->bRxInt == TRUE) 02125 { 02126 pstcMfsInternData->stcCsioInternIntCb.pfnRxIntCb = pstcIntCb->pfnRxIntCb; 02127 pstcCsio->SCR_f.RIE = 1; 02128 } 02129 02130 if(pstcInt->bTxInt == TRUE) 02131 { 02132 pstcMfsInternData->stcCsioInternIntCb.pfnTxIntCb = pstcIntCb->pfnTxIntCb; 02133 pstcCsio->SCR_f.TIE = 1; 02134 } 02135 02136 if(pstcInt->bTxIdle == TRUE) 02137 { 02138 pstcMfsInternData->stcCsioInternIntCb.pfnTxIdleCb = pstcIntCb->pfnTxIdleCb; 02139 pstcCsio->SCR_f.TBIE = 1; 02140 } 02141 02142 if(pstcInt->bTxFifoInt == TRUE) 02143 { 02144 pstcMfsInternData->stcCsioInternIntCb.pfnTxFifoIntCb = pstcIntCb->pfnTxFifoIntCb; 02145 pstcCsio->FCR1_f.FTIE = 1; 02146 } 02147 02148 if(pstcInt->bCsErrInt == TRUE) 02149 { 02150 pstcMfsInternData->stcCsioInternIntCb.pfnCsErrIntCb = pstcIntCb->pfnCsErrIntCb; 02151 pstcCsio->SACSR_f.CSEIE = 1; 02152 } 02153 02154 if(pstcInt->bSerialTimerInt == TRUE) 02155 { 02156 pstcMfsInternData->stcCsioInternIntCb.pfnSerialTimerIntCb = pstcIntCb->pfnSerialTimerIntCb; 02157 pstcCsio->SACSR_f.TINTE = 1; 02158 } 02159 02160 if(pstcInt->bRxInt == TRUE) 02161 { 02162 Mfs_InitIrq(enIndex, FALSE); 02163 } 02164 02165 if((pstcInt->bTxInt == TRUE) || (pstcInt->bTxIdle == TRUE) || 02166 (pstcInt->bTxFifoInt == TRUE) || (pstcInt->bCsErrInt == TRUE) || 02167 (pstcInt->bSerialTimerInt == TRUE)) 02168 { 02169 Mfs_InitIrq(enIndex, TRUE); 02170 } 02171 02172 return Ok; 02173 } 02174 02192 en_result_t Mfs_Csio_DisableInt(volatile stc_mfsn_csio_t* pstcCsio, 02193 stc_csio_int_sel_t* pstcInt) 02194 { 02195 stc_mfs_intern_data_t* pstcMfsInternData; 02196 en_mfs_instance_index_t enIndex; 02197 uint8_t u8Ch; 02198 02199 /* Check for valid pointer and get pointer to internal data struct ... */ 02200 pstcMfsInternData = MfsCsioGetInternDataPtr(pstcCsio); 02201 enIndex = MfsCsioGetInstanceIndex(pstcCsio); 02202 02203 if ((NULL == pstcMfsInternData) || 02204 (NULL == pstcInt) || 02205 (MfsInstanceIndexUnknown == enIndex) ) 02206 { 02207 return (ErrorInvalidParameter); 02208 } 02209 02210 u8Ch = CsioInstanceToIndex(pstcCsio); 02211 02212 if(pstcInt->bRxInt == TRUE) 02213 { 02214 pstcMfsInternData->stcCsioInternIntCb.pfnRxIntCb = NULL; 02215 pstcCsio->SCR_f.RIE = 0; 02216 } 02217 02218 if(pstcInt->bTxInt == TRUE) 02219 { 02220 pstcMfsInternData->stcCsioInternIntCb.pfnTxIntCb = NULL; 02221 pstcCsio->SCR_f.TIE = 0; 02222 } 02223 02224 if(pstcInt->bTxIdle == TRUE) 02225 { 02226 pstcMfsInternData->stcCsioInternIntCb.pfnTxIdleCb = NULL; 02227 pstcCsio->SCR_f.TBIE = 0; 02228 } 02229 02230 if(pstcInt->bTxFifoInt == TRUE) 02231 { 02232 pstcMfsInternData->stcCsioInternIntCb.pfnTxFifoIntCb = NULL; 02233 pstcCsio->FCR1_f.FTIE = 0; 02234 } 02235 02236 if(pstcInt->bCsErrInt == TRUE) 02237 { 02238 pstcMfsInternData->stcCsioInternIntCb.pfnCsErrIntCb = NULL; 02239 pstcCsio->SACSR_f.CSEIE = 0; 02240 } 02241 02242 if(pstcInt->bSerialTimerInt == TRUE) 02243 { 02244 pstcMfsInternData->stcCsioInternIntCb.pfnSerialTimerIntCb = NULL; 02245 pstcCsio->SACSR_f.TINTE = 0; 02246 } 02247 02248 // Only when RX interrupts and DMA interrupt(share same IRQ with MFS ch.14, ch.15) 02249 // are all disabled, disable RX IRQ 02250 do 02251 { 02252 if(pstcCsio->SCR_f.RIE == 1) 02253 { 02254 break; 02255 } 02256 02257 if(u8Ch == 14u) 02258 { 02259 if((FM0P_DMAC->DMACB0_f.CI == 1) || (FM0P_DMAC->DMACB0_f.EI == 1)) 02260 { 02261 break; 02262 } 02263 } 02264 02265 if(u8Ch == 15u) 02266 { 02267 if((FM0P_DMAC->DMACB2_f.CI == 1) || (FM0P_DMAC->DMACB2_f.EI == 1)) 02268 { 02269 break; 02270 } 02271 } 02272 02273 Mfs_DeInitIrq(enIndex, FALSE); 02274 02275 }while(0); 02276 02277 // Only when TX interrupts and DMA interrupt(share same IRQ with MFS ch.14, ch.15) 02278 // are all disabled, disable TX IRQ 02279 do 02280 { 02281 if(pstcCsio->SCR_f.TIE == 1) 02282 { 02283 break; 02284 } 02285 02286 if(pstcCsio->SCR_f.TBIE == 1) 02287 { 02288 break; 02289 } 02290 02291 if(pstcCsio->FCR1_f.FTIE == 1) 02292 { 02293 break; 02294 } 02295 02296 if(pstcCsio->SACSR_f.CSEIE == 1) 02297 { 02298 break; 02299 } 02300 02301 if(pstcCsio->SACSR_f.TINTE == 1) 02302 { 02303 break; 02304 } 02305 02306 if(u8Ch == 14u) 02307 { 02308 if((FM0P_DMAC->DMACB1_f.CI == 0) && (FM0P_DMAC->DMACB1_f.EI == 0)) 02309 { 02310 break; 02311 } 02312 } 02313 02314 if(u8Ch == 15u) 02315 { 02316 if((FM0P_DMAC->DMACB3_f.CI == 0) && (FM0P_DMAC->DMACB3_f.EI == 0)) 02317 { 02318 break; 02319 } 02320 } 02321 02322 Mfs_DeInitIrq(enIndex, TRUE); 02323 02324 }while(0); 02325 02326 return Ok; 02327 } 02328 02329 #endif 02330 02348 en_result_t Mfs_Csio_Init(volatile stc_mfsn_csio_t* pstcCsio, 02349 const stc_mfs_csio_config_t* pstcConfig) 02350 { 02351 stc_mfs_intern_data_t* pstcMfsInternData; 02352 02353 /* Preset local register variables to zero */ 02354 stc_mfs_csio_smr_field_t stcSMR = { 0 }; 02355 stc_mfs_csio_scr_field_t stcSCR = { 0 }; 02356 stc_mfs_csio_ssr_field_t stcSSR = { 0 }; 02357 stc_mfs_csio_escr_field_t stcESCR = { 0 }; 02358 02359 /* Check for valid pointer and get pointer to internal data struct ... */ 02360 pstcMfsInternData = MfsCsioGetInternDataPtr(pstcCsio); 02361 02362 /* Parameter check and get ptr to internal data struct */ 02363 if ((NULL == pstcMfsInternData) 02364 || (NULL == pstcConfig)) 02365 { 02366 return (ErrorInvalidParameter); 02367 } 02368 02369 /* Set MFS mode in the internal structure */ 02370 pstcMfsInternData->enMode = MfsCsioMode; 02371 02372 /* Set CSIO mode */ 02373 stcSMR.MD = 2u; 02374 02375 /* Set master/slave mode */ 02376 switch(pstcConfig->enMsMode) 02377 { 02378 case CsioMaster: 02379 stcSCR.MS = FALSE; /* Master mode */ 02380 /* Enable SOE */ 02381 stcSMR.SOE = TRUE; 02382 /* Enable SCKE */ 02383 stcSMR.SCKE = TRUE; 02384 break; 02385 case CsioSlave: 02386 stcSCR.MS = TRUE; /* Slave mode */ 02387 /* Enable SOE */ 02388 stcSMR.SOE = TRUE; 02389 /* Enable SCKE */ 02390 stcSMR.SCKE = FALSE; /* Disable clock output in slave mode */ 02391 break; 02392 default: 02393 return ErrorInvalidParameter; 02394 } 02395 02396 02397 02398 /* Set normal/SPI mode */ 02399 switch (pstcConfig->enActMode) 02400 { 02401 case CsioActNormalMode: 02402 stcSCR.SPI = FALSE; /* Normal mode */ 02403 break; 02404 case CsioActSpiMode: 02405 stcSCR.SPI = TRUE; /* SPI mode */ 02406 break; 02407 default: 02408 return (ErrorInvalidParameter); 02409 } 02410 02411 /* Wait time insertion */ 02412 switch(pstcConfig->enSyncWaitTime) 02413 { 02414 case CsioSyncWaitZero: 02415 stcESCR.WT = 0u; /* 0bit */ 02416 break; 02417 case CsioSyncWaitOne: 02418 stcESCR.WT = 1u; /* 1bit */ 02419 break; 02420 case CsioSyncWaitTwo: 02421 stcESCR.WT = 2u; /* 2bits */ 02422 break; 02423 case CsioSyncWaitThree: 02424 stcESCR.WT = 3u; /* 3bits */ 02425 break; 02426 default: 02427 return (ErrorInvalidParameter); 02428 } 02429 02430 stcESCR.L3 = 0; /* Default:less than 13 bits */ 02431 02432 /* Set Data bit length (5-16 bits) */ 02433 switch (pstcConfig->enDataLength) 02434 { 02435 case CsioFiveBits: 02436 stcESCR.L = 1u; 02437 break; 02438 case CsioSixBits: 02439 stcESCR.L = 2u; 02440 break; 02441 case CsioSevenBits: 02442 stcESCR.L = 3u; 02443 break; 02444 case CsioEightBits: 02445 stcESCR.L = 0u; 02446 break; 02447 case CsioNineBits: 02448 stcESCR.L = 4u; 02449 break; 02450 case CsioTenBits: 02451 stcESCR.L = 5u; 02452 break; 02453 case CsioElevenBits: 02454 stcESCR.L = 6u; 02455 break; 02456 case CsioTwelveBits: 02457 stcESCR.L = 7u; 02458 break; 02459 case CsioThirteenBits: 02460 stcESCR.L = 0u; 02461 stcESCR.L3 = TRUE; /* More than 12 bits */ 02462 break; 02463 case CsioFourteenBits: 02464 stcESCR.L = 1u; 02465 stcESCR.L3 = TRUE; /* More than 12 bits */ 02466 break; 02467 case CsioFifteenBits: 02468 stcESCR.L = 2u; 02469 stcESCR.L3 = TRUE; /* More than 12 bits */ 02470 break; 02471 case CsioSixteenBits: 02472 stcESCR.L = 3u; 02473 stcESCR.L3 = TRUE; /* More than 12 bits */ 02474 break; 02475 default: 02476 return (ErrorInvalidParameter); 02477 } 02478 /* Set Bit direction (LSB/MSB) */ 02479 switch(pstcConfig->enBitDirection) 02480 { 02481 case CsioDataLsbFirst: 02482 stcSMR.BDS = FALSE; 02483 break; 02484 case CsioDataMsbFirst: 02485 stcSMR.BDS = TRUE; 02486 break; 02487 default: 02488 return ErrorInvalidParameter; 02489 } 02490 02491 /* Set Signal system (SCK Mark Level) */ 02492 if (TRUE == pstcConfig->bInvertClk) 02493 { 02494 stcSMR.SCINV = TRUE; /* SCK Make Level : Low */ 02495 } 02496 else 02497 { 02498 stcSMR.SCINV = FALSE; /* SCK Make Level : High */ 02499 } 02500 02501 stcSSR.REC = TRUE; /* Clear received error flag */ 02502 02503 /* Set Baudrate */ 02504 (void)Mfs_Csio_SetBaudRate(pstcCsio, pstcConfig->u32BaudRate); 02505 /* Set registers value */ 02506 pstcCsio->SMR_f = stcSMR; 02507 pstcCsio->SCR_f = stcSCR; 02508 pstcCsio->ESCR_f = stcESCR; 02509 pstcCsio->SSR_f = stcSSR; 02510 02511 if(pstcConfig->bEnSyncTransfer == TRUE) /* Use serial timer? */ 02512 { 02513 /* Set serial timer clock */ 02514 switch(pstcConfig->stcSerialTimer.enClkDiv) 02515 { 02516 case CsioTimerNoDiv: 02517 pstcCsio->SACSR_f.TDIV = 0u; 02518 break; 02519 case CsioTimerDiv2: 02520 pstcCsio->SACSR_f.TDIV = 1u; 02521 break; 02522 case CsioTimerDiv4: 02523 pstcCsio->SACSR_f.TDIV = 2u; 02524 break; 02525 case CsioTimerDiv8: 02526 pstcCsio->SACSR_f.TDIV = 3u; 02527 break; 02528 case CsioTimerDiv16: 02529 pstcCsio->SACSR_f.TDIV = 4u; 02530 break; 02531 case CsioTimerDiv32: 02532 pstcCsio->SACSR_f.TDIV = 5u; 02533 break; 02534 case CsioTimerDiv64: 02535 pstcCsio->SACSR_f.TDIV = 6u; 02536 break; 02537 case CsioTimerDiv128: 02538 pstcCsio->SACSR_f.TDIV = 7u; 02539 break; 02540 case CsioTimerDiv256: 02541 pstcCsio->SACSR_f.TDIV = 8u; 02542 break; 02543 default: 02544 return ErrorInvalidParameter; 02545 } 02546 02547 /* Transfer count */ 02548 pstcCsio->TBYTE0 = pstcConfig->stcSerialTimer.u8TransferByteCnt; 02549 02550 /* Timer compare value */ 02551 pstcCsio->STMCR = pstcConfig->stcSerialTimer.u16CompareVal; 02552 02553 /* Enable sync transfer */ 02554 pstcCsio->SACSR_f.TSYNE = 1; 02555 } 02556 02557 if(pstcConfig->bEnChipSelection == TRUE) /* Use chip selection function? */ 02558 { 02559 if(pstcConfig->enMsMode == CsioMaster) 02560 { 02561 /* Select CS start pin */ 02562 switch(pstcConfig->stcCsConfig.enCsStartPin) 02563 { 02564 case CsPinScs0: 02565 pstcCsio->SCSCR_f.SST = 0u; 02566 break; 02567 case CsPinScs1: 02568 pstcCsio->SCSCR_f.SST = 1u; 02569 break; 02570 case CsPinScs2: 02571 pstcCsio->SCSCR_f.SST = 2u; 02572 break; 02573 case CsPinScs3: 02574 pstcCsio->SCSCR_f.SST = 3u; 02575 break; 02576 default: 02577 return ErrorInvalidParameter; 02578 } 02579 02580 /* Select CS end pin */ 02581 switch(pstcConfig->stcCsConfig.enCsEndPin) 02582 { 02583 case CsPinScs0: 02584 pstcCsio->SCSCR_f.SED = 0u; 02585 break; 02586 case CsPinScs1: 02587 pstcCsio->SCSCR_f.SED = 1u; 02588 break; 02589 case CsPinScs2: 02590 pstcCsio->SCSCR_f.SED = 2u; 02591 break; 02592 case CsPinScs3: 02593 pstcCsio->SCSCR_f.SED = 3u; 02594 break; 02595 default: 02596 return ErrorInvalidParameter; 02597 } 02598 02599 /* Set transfer count of each SCS pin */ 02600 pstcCsio->TBYTE0 = pstcConfig->stcCsConfig.u8Scs0TransferByteCnt; 02601 pstcCsio->TBYTE1 = pstcConfig->stcCsConfig.u8Scs1TransferByteCnt; 02602 pstcCsio->TBYTE2 = pstcConfig->stcCsConfig.u8Scs2TransferByteCnt; 02603 pstcCsio->TBYTE3 = pstcConfig->stcCsConfig.u8Scs3TransferByteCnt; 02604 02605 /* Select CS active level (only for SCS0) */ 02606 switch(pstcConfig->stcCsConfig.enLevel) 02607 { 02608 case CsHighActive: 02609 pstcCsio->SCSCR_f.CSLVL = 0; 02610 break; 02611 case CsLowActive: 02612 pstcCsio->SCSCR_f.CSLVL = 1; 02613 break; 02614 default: 02615 return ErrorInvalidParameter; 02616 } 02617 02618 /* Active hold or not */ 02619 pstcCsio->SCSCR_f.SCAM = pstcConfig->stcCsConfig.bActiveHold; 02620 02621 /* Set chip selection clock */ 02622 switch(pstcConfig->stcCsConfig.enClkDiv) 02623 { 02624 case CsClkNoDiv: 02625 pstcCsio->SCSCR_f.CDIV = 0u; 02626 break; 02627 case CsClkDiv2: 02628 pstcCsio->SCSCR_f.CDIV = 1u; 02629 break; 02630 case CsClkDiv4: 02631 pstcCsio->SCSCR_f.CDIV = 2u; 02632 break; 02633 case CsClkDiv8: 02634 pstcCsio->SCSCR_f.CDIV = 3u; 02635 break; 02636 case CsClkDiv16: 02637 pstcCsio->SCSCR_f.CDIV = 4u; 02638 break; 02639 case CsClkDiv32: 02640 pstcCsio->SCSCR_f.CDIV = 5u; 02641 break; 02642 case CsClkDiv64: 02643 pstcCsio->SCSCR_f.CDIV = 6u; 02644 break; 02645 default: 02646 return ErrorInvalidParameter; 02647 } 02648 /* Set chip selection timing */ 02649 pstcCsio->SCSTR1 = pstcConfig->stcCsConfig.u8CsSetupDelayTime; 02650 pstcCsio->SCSTR0 = pstcConfig->stcCsConfig.u8CsHoldDelayTime; 02651 pstcCsio->SCSTR32 = pstcConfig->stcCsConfig.u16CsDeselectTime; 02652 } 02653 02654 /* Enable SCS pin */ 02655 pstcCsio->SCSCR_f.CSEN0 = ((pstcConfig->stcCsConfig.bScs0En == TRUE) ? 1 : 0); 02656 pstcCsio->SCSCR_f.CSEN1 = ((pstcConfig->stcCsConfig.bScs1En == TRUE) ? 1 : 0); 02657 pstcCsio->SCSCR_f.CSEN2 = ((pstcConfig->stcCsConfig.bScs2En == TRUE) ? 1 : 0); 02658 pstcCsio->SCSCR_f.CSEN3 = ((pstcConfig->stcCsConfig.bScs3En == TRUE) ? 1 : 0); 02659 02660 if(pstcConfig->enMsMode == CsioMaster) 02661 { 02662 /* Enable CS pins output */ 02663 pstcCsio->SCSCR_f.CSOE = 1; 02664 } 02665 else 02666 { 02667 /* Disable CS pins output */ 02668 pstcCsio->SCSCR_f.CSOE = 0; 02669 } 02670 } 02671 02672 if(pstcConfig->bEnableFifo == TRUE) /* Use FIFO function? */ 02673 { 02674 /* Reset FIFO */ 02675 pstcCsio->FCR0_f.FCL1 = 1; 02676 pstcCsio->FCR0_f.FCL2 = 1; 02677 /* Enable FIFO receive Idle detection */ 02678 pstcCsio->FCR1_f.FRIIE = 1; 02679 /* Selection TX and RX FIFO */ 02680 switch(pstcConfig->stcFifoConfig.enFifoSel) 02681 { 02682 case MfsTxFifo1RxFifo2: 02683 pstcCsio->FCR1_f.FSEL = 0; 02684 break; 02685 case MfsTxFifo2RxFifo1: 02686 pstcCsio->FCR1_f.FSEL = 1; 02687 break; 02688 default: 02689 return (ErrorInvalidParameter); 02690 } 02691 /* Set FIFO count */ 02692 pstcCsio->FBYTE1 = pstcConfig->stcFifoConfig.u8ByteCount1; 02693 pstcCsio->FBYTE2 = pstcConfig->stcFifoConfig.u8ByteCount2; 02694 /* Enable FIFO */ 02695 pstcCsio->FCR0_f.FE1 = 1; 02696 pstcCsio->FCR0_f.FE2 = 1; 02697 } 02698 02699 return (Ok); 02700 } /* Mfs_Csio_Init */ 02701 02717 en_result_t Mfs_Csio_DeInit(volatile stc_mfsn_csio_t* pstcCsio) 02718 { 02719 en_result_t enResult; 02720 stc_mfs_intern_data_t* pstcMfsInternData; 02721 02722 /* Check for valid pointer and get pointer to internal data struct ... */ 02723 pstcMfsInternData = MfsCsioGetInternDataPtr(pstcCsio); 02724 /* ... and check */ 02725 if (NULL == pstcMfsInternData) 02726 { 02727 enResult = ErrorInvalidParameter; 02728 } 02729 else 02730 { 02731 /* First of all disable receiver, transmitter and deinit interrupts */ 02732 pstcCsio->SCR_f.TXE = FALSE; 02733 pstcCsio->SCR_f.RXE = FALSE; 02734 02735 /* Baud Rate Generation Reload Reset */ 02736 pstcCsio->BGR = 0u; 02737 02738 /* Serial Mode Register clear all bits (valid in any mode) */ 02739 pstcCsio->SMR = 0u; 02740 02741 /* Reset Mfs receive and transmit bit to default */ 02742 /* and clear all error flags */ 02743 pstcCsio->SCR = 0u; 02744 02745 /* Clear reception Errors */ 02746 pstcCsio->SSR_f.REC = TRUE; 02747 02748 /* Reset all other used register to default value */ 02749 pstcCsio->SSR = 0u; 02750 pstcCsio->ESCR = 0u; 02751 pstcCsio->FCR0 = 0u; 02752 pstcCsio->FCR1 = 0u; 02753 pstcCsio->SACSR = 0u; 02754 pstcCsio->STMCR = 0u; 02755 pstcCsio->SCSCR = 0u; 02756 pstcCsio->SCSTR0 = 0; 02757 pstcCsio->SCSTR1 = 0; 02758 pstcCsio->SCSTR32 = 0; 02759 pstcCsio->TBYTE0 = 0u; 02760 pstcCsio->TBYTE1 = 0u; 02761 pstcCsio->TBYTE2 = 0u; 02762 pstcCsio->TBYTE3 = 0u; 02763 02764 enResult = Ok; 02765 } 02766 02767 return (enResult); 02768 } /* Mfs_Csio_DeInit */ 02769 02786 en_result_t Mfs_Csio_SetBaudRate(volatile stc_mfsn_csio_t* pstcCsio, 02787 uint32_t u32BaudRate) 02788 { 02789 uint32_t u32Pclk1; 02790 02791 if ((NULL == pstcCsio) || (u32BaudRate < 3)) 02792 { 02793 return ErrorInvalidParameter; 02794 } 02795 02796 u32Pclk1 = __HCLK/(1ul << (APBC1_PSR_Val & 0x03u)); /* MFS is attached on APB1 bus */ 02797 02798 pstcCsio->BGR_f.BGR = (u32Pclk1/u32BaudRate) - 1; 02799 02800 return Ok; 02801 } 02802 02819 en_result_t Mfs_Csio_SetTimerCompareValue(volatile stc_mfsn_csio_t* pstcCsio, 02820 uint16_t u16CompareValue) 02821 { 02822 if (NULL == pstcCsio) 02823 { 02824 return ErrorInvalidParameter; 02825 } 02826 02827 pstcCsio->STMCR = u16CompareValue; 02828 02829 return Ok; 02830 } 02831 02849 en_result_t Mfs_Csio_SetCsTransferByteCount(volatile stc_mfsn_csio_t* pstcCsio, 02850 en_cs_pin_sel_t enCsPin, 02851 uint8_t u8ByteCnt) 02852 { 02853 if (NULL == pstcCsio) 02854 { 02855 return ErrorInvalidParameter; 02856 } 02857 02858 switch(enCsPin) 02859 { 02860 case CsPinScs0: 02861 pstcCsio->TBYTE0 = u8ByteCnt; 02862 break; 02863 case CsPinScs1: 02864 pstcCsio->TBYTE1 = u8ByteCnt; 02865 break; 02866 case CsPinScs2: 02867 pstcCsio->TBYTE2 = u8ByteCnt; 02868 break; 02869 case CsPinScs3: 02870 pstcCsio->TBYTE3 = u8ByteCnt; 02871 break; 02872 default: 02873 return ErrorInvalidParameter; 02874 } 02875 02876 return Ok; 02877 } 02878 02895 en_result_t Mfs_Csio_SetCsHoldStatus(volatile stc_mfsn_csio_t* pstcCsio, 02896 boolean_t bHold) 02897 { 02898 if (NULL == pstcCsio) 02899 { 02900 return ErrorInvalidParameter; 02901 } 02902 02903 pstcCsio->SCSCR_f.SCAM = (bHold == TRUE) ? 1 : 0; 02904 02905 return Ok; 02906 } 02907 02924 en_result_t Mfs_Csio_SetTimerTransferByteCount(volatile stc_mfsn_csio_t* pstcCsio, 02925 uint8_t u8ByteCnt) 02926 { 02927 if (NULL == pstcCsio) 02928 { 02929 return ErrorInvalidParameter; 02930 } 02931 02932 pstcCsio->TBYTE0 = u8ByteCnt; 02933 02934 return Ok; 02935 } 02936 02953 en_result_t Mfs_Csio_EnableFunc(volatile stc_mfsn_csio_t* pstcCsio, en_csio_func_t enFunc) 02954 { 02955 if (NULL == pstcCsio) 02956 { 02957 return ErrorInvalidParameter; 02958 } 02959 02960 switch(enFunc) 02961 { 02962 case CsioTx: 02963 pstcCsio->SCR_f.TXE = 1; 02964 break; 02965 case CsioRx: 02966 pstcCsio->SCR_f.RXE = 1; 02967 break; 02968 case CsioSerialTimer: 02969 pstcCsio->SACSR_f.TMRE = 1; 02970 break; 02971 case CsioCsErrOccur: 02972 pstcCsio->SACSR_f.TBEEN = 1; 02973 break; 02974 default: 02975 return ErrorInvalidParameter; 02976 } 02977 02978 return Ok; 02979 } 02980 02997 en_result_t Mfs_Csio_DisableFunc(volatile stc_mfsn_csio_t* pstcCsio, en_csio_func_t enFunc) 02998 { 02999 if (NULL == pstcCsio) 03000 { 03001 return ErrorInvalidParameter; 03002 } 03003 03004 switch(enFunc) 03005 { 03006 case CsioTx: 03007 pstcCsio->SCR_f.TXE = 0; 03008 break; 03009 case CsioRx: 03010 pstcCsio->SCR_f.RXE = 0; 03011 break; 03012 case CsioSerialTimer: 03013 pstcCsio->SACSR_f.TMRE = 0; 03014 break; 03015 case CsioCsErrOccur: 03016 pstcCsio->SACSR_f.TBEEN = 0; 03017 break; 03018 default: 03019 return ErrorInvalidParameter; 03020 } 03021 03022 return Ok; 03023 } 03024 03057 boolean_t Mfs_Csio_GetStatus(volatile stc_mfsn_csio_t* pstcCsio, 03058 en_csio_status_t enStatus) 03059 { 03060 boolean_t bRet = FALSE; 03061 03062 switch(enStatus) 03063 { 03064 case CsioOverrunError: 03065 bRet = (pstcCsio->SSR_f.ORE == 1) ? TRUE : FALSE; 03066 break; 03067 case CsioRxFull: 03068 bRet = (pstcCsio->SSR_f.RDRF == 1) ? TRUE : FALSE; 03069 break; 03070 case CsioTxEmpty: 03071 bRet = (pstcCsio->SSR_f.TDRE == 1) ? TRUE : FALSE; 03072 break; 03073 case CsioTxIdle: 03074 bRet = (pstcCsio->SSR_f.TBI == 1) ? TRUE : FALSE; 03075 break; 03076 case CsioTxFifoRequest: 03077 bRet = (pstcCsio->FCR1_f.FDRQ == 1) ? TRUE : FALSE; 03078 break; 03079 case CsioCsErrIntFlag: 03080 bRet = (pstcCsio->SACSR_f.CSE == 1) ? TRUE : FALSE; 03081 break; 03082 case CsioTimerIntFlag: 03083 bRet = (pstcCsio->SACSR_f.TINT == 1) ? TRUE : FALSE; 03084 break; 03085 default: 03086 break; 03087 } 03088 03089 return bRet; 03090 } 03091 03114 en_result_t Mfs_Csio_ClrStatus(volatile stc_mfsn_csio_t* pstcCsio, 03115 en_csio_status_t enStatus) 03116 { 03117 if (NULL == pstcCsio) 03118 { 03119 return ErrorInvalidParameter; 03120 } 03121 03122 switch(enStatus) 03123 { 03124 case CsioOverrunError: 03125 pstcCsio->SSR_f.REC = 1; 03126 break; 03127 case CsioRxFull: 03128 case CsioTxEmpty: 03129 case CsioTxIdle: 03130 break; 03131 case CsioTxFifoRequest: 03132 pstcCsio->FCR1_f.FDRQ = 0; 03133 break; 03134 case CsioCsErrIntFlag: 03135 pstcCsio->SACSR_f.CSE = 0;; 03136 break; 03137 case CsioTimerIntFlag: 03138 pstcCsio->SACSR_f.TINT = 0; 03139 break; 03140 default: 03141 return ErrorInvalidParameter; 03142 } 03143 03144 return Ok; 03145 } 03146 03162 en_result_t Mfs_Csio_SendData(volatile stc_mfsn_csio_t* pstcCsio, 03163 uint16_t u16Data, 03164 boolean_t bSotEn) 03165 { 03166 if (NULL == pstcCsio) 03167 { 03168 return ErrorInvalidParameter; 03169 } 03170 03171 (bSotEn == TRUE) ? (pstcCsio->SMR_f.SOE = 1) : (pstcCsio->SMR_f.SOE = 0); 03172 03173 pstcCsio->TDR = u16Data; 03174 03175 return Ok; 03176 } 03177 03187 uint16_t Mfs_Csio_ReceiveData(volatile stc_mfsn_csio_t* pstcCsio) 03188 { 03189 return pstcCsio->RDR; 03190 } 03191 03204 en_result_t Mfs_Csio_ResetFifo (volatile stc_mfsn_csio_t* pstcCsio, 03205 en_mfs_fifo_t enFifo) 03206 { 03207 if (NULL == pstcCsio) 03208 { 03209 return ErrorInvalidParameter; 03210 } 03211 03212 switch(enFifo) 03213 { 03214 case MfsFifo1: 03215 pstcCsio->FCR0_f.FCL1 = 1; 03216 break; 03217 case MfsFifo2: 03218 pstcCsio->FCR0_f.FCL2 = 1; 03219 break; 03220 default: 03221 return ErrorInvalidParameter; 03222 } 03223 03224 return Ok; 03225 } 03226 03240 en_result_t Mfs_Csio_SetFifoCount(volatile stc_mfsn_csio_t* pstcCsio, 03241 en_mfs_fifo_t enFifo, 03242 uint8_t u8Count) 03243 { 03244 if (NULL == pstcCsio) 03245 { 03246 return ErrorInvalidParameter; 03247 } 03248 03249 switch(enFifo) 03250 { 03251 case MfsFifo1: 03252 pstcCsio->FBYTE1 = u8Count; 03253 break; 03254 case MfsFifo2: 03255 pstcCsio->FBYTE2 = u8Count; 03256 break; 03257 default: 03258 return ErrorInvalidParameter; 03259 } 03260 03261 return Ok; 03262 } 03263 03278 uint8_t Mfs_Csio_GetFifoCount(volatile stc_mfsn_csio_t* pstcCsio, 03279 en_mfs_fifo_t enFifo) 03280 { 03281 uint8_t u8FifoCnt = 0xFFu; 03282 03283 switch(enFifo) 03284 { 03285 case MfsFifo1: 03286 u8FifoCnt = pstcCsio->FBYTE1; 03287 break; 03288 case MfsFifo2: 03289 u8FifoCnt = pstcCsio->FBYTE2; 03290 break; 03291 default: 03292 break; 03293 } 03294 03295 return u8FifoCnt; 03296 } 03297 03298 /****************************************************************************** 03299 * I2C driver functions 03300 ******************************************************************************/ 03301 03311 static stc_mfs_intern_data_t* MfsI2cGetInternDataPtr(volatile stc_mfsn_i2c_t* pstcI2c) 03312 { 03313 stc_mfs_intern_data_t* pstcInternDataPtr = NULL; 03314 uint32_t u32Instance; 03315 03316 if (NULL != pstcI2c) 03317 { 03318 for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) 03319 { 03320 if (pstcI2c == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcI2cInstance) 03321 { 03322 pstcInternDataPtr = &m_astcMfsInstanceDataLut[u32Instance].stcInternData; 03323 break; 03324 } 03325 } 03326 03327 } 03328 03329 return (pstcInternDataPtr); 03330 } /* MfsGetInternDataPtr */ 03331 03332 03333 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ 03334 (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ 03335 (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ 03336 (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ 03337 (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ 03338 (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ 03339 (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ 03340 (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 03341 03350 static en_mfs_instance_index_t MfsI2cGetInstanceIndex(volatile stc_mfsn_i2c_t* pstcI2c) 03351 { 03352 en_mfs_instance_index_t enInstanceIndex = MfsInstanceIndexUnknown; 03353 uint32_t u32Instance; 03354 03355 if (NULL != pstcI2c) 03356 { 03357 for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) 03358 { 03359 if (pstcI2c == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcI2cInstance) 03360 { 03361 enInstanceIndex = m_astcMfsInstanceDataLut[u32Instance].stcInternData.enIndex; 03362 break; 03363 } 03364 } 03365 03366 } 03367 03368 return (enInstanceIndex); 03369 } /* MfsI2cGetInstanceIndex */ 03370 03371 03382 void MfsI2cIrqHandlerRx( volatile stc_mfsn_i2c_t* pstcI2c, 03383 stc_mfs_intern_data_t* pstcMfsInternData) 03384 { 03385 if ((NULL != pstcI2c) && (NULL != pstcMfsInternData)) 03386 { 03387 if (NULL != pstcMfsInternData->stcI2cInternIntCb.pfnRxIntCb) 03388 { 03389 pstcMfsInternData->stcI2cInternIntCb.pfnRxIntCb(); 03390 } 03391 } 03392 } /* MfsIrqHandlerRx */ 03393 03404 void MfsI2cIrqHandlerTx( volatile stc_mfsn_i2c_t* pstcI2c, 03405 stc_mfs_intern_data_t* pstcMfsInternData) 03406 { 03407 if(pstcI2c->SSR_f.TDRE == 1) 03408 { 03409 if (NULL != pstcMfsInternData->stcI2cInternIntCb.pfnTxIntCb) 03410 { 03411 pstcMfsInternData->stcI2cInternIntCb.pfnTxIntCb(); 03412 } 03413 } 03414 03415 if(pstcI2c->SSR_f.TBI == 1) 03416 { 03417 if (NULL != pstcMfsInternData->stcI2cInternIntCb.pfnTxIdleCb) 03418 { 03419 pstcMfsInternData->stcI2cInternIntCb.pfnTxIdleCb(); 03420 } 03421 } 03422 03423 if(pstcI2c->FCR1_f.FDRQ == 1) 03424 { 03425 if (NULL != pstcMfsInternData->stcI2cInternIntCb.pfnTxFifoIntCb) 03426 { 03427 pstcMfsInternData->stcI2cInternIntCb.pfnTxFifoIntCb(); 03428 } 03429 03430 pstcI2c->FCR1_f.FDRQ = 0; 03431 } 03432 } /* MfsIrqHandlerTx */ 03433 03444 void MfsI2cIrqHandlerStatus( volatile stc_mfsn_i2c_t* pstcI2c, 03445 stc_mfs_intern_data_t* pstcMfsInternData) 03446 { 03447 if ((NULL != pstcI2c) && (NULL != pstcMfsInternData)) 03448 { 03449 if(pstcI2c->IBCR_f.INT == 1) 03450 { 03451 if (NULL != pstcMfsInternData->stcI2cInternIntCb.pfnTxRxCb) 03452 { 03453 pstcMfsInternData->stcI2cInternIntCb.pfnTxRxCb(); 03454 } 03455 03456 pstcI2c->IBCR_f.INT = 0; 03457 } 03458 03459 if(pstcI2c->IBSR_f.SPC == 1) 03460 { 03461 if (NULL != pstcMfsInternData->stcI2cInternIntCb.pfnStopDetectCb) 03462 { 03463 pstcMfsInternData->stcI2cInternIntCb.pfnStopDetectCb(); 03464 } 03465 03466 pstcI2c->IBSR_f.SPC = 0; 03467 } 03468 } 03469 } 03470 03491 en_result_t Mfs_I2c_EnableInt(volatile stc_mfsn_i2c_t* pstcI2c, 03492 stc_i2c_int_sel_t* pstcInt, 03493 stc_i2c_int_cb_t* pstcIntCb) 03494 { 03495 stc_mfs_intern_data_t* pstcMfsInternData; 03496 en_mfs_instance_index_t enIndex; 03497 03498 /* Check for valid pointer and get pointer to internal data struct ... */ 03499 pstcMfsInternData = MfsI2cGetInternDataPtr(pstcI2c); 03500 enIndex = MfsI2cGetInstanceIndex(pstcI2c); 03501 03502 if ((NULL == pstcMfsInternData) || 03503 (NULL == pstcInt) || 03504 (NULL == pstcIntCb) || 03505 (MfsInstanceIndexUnknown == enIndex) ) 03506 { 03507 return (ErrorInvalidParameter); 03508 } 03509 03510 if(pstcInt->bTxInt == TRUE) 03511 { 03512 pstcMfsInternData->stcI2cInternIntCb.pfnTxIntCb = pstcIntCb->pfnTxIntCb; 03513 pstcI2c->SMR_f.TIE = 1; 03514 } 03515 03516 if(pstcInt->bRxInt == TRUE) 03517 { 03518 pstcMfsInternData->stcI2cInternIntCb.pfnRxIntCb = pstcIntCb->pfnRxIntCb; 03519 pstcI2c->SMR_f.RIE = 1; 03520 } 03521 03522 if(pstcInt->bTxFifoInt == TRUE) 03523 { 03524 pstcMfsInternData->stcI2cInternIntCb.pfnTxFifoIntCb = pstcIntCb->pfnTxFifoIntCb; 03525 pstcI2c->FCR1_f.FTIE = 1; 03526 } 03527 03528 if(pstcInt->bTxIdle == TRUE) 03529 { 03530 pstcMfsInternData->stcI2cInternIntCb.pfnTxIdleCb = pstcIntCb->pfnTxIdleCb; 03531 pstcI2c->SSR_f.TBIE = 1; 03532 } 03533 03534 if(pstcInt->bTxRxInt == TRUE) 03535 { 03536 pstcMfsInternData->stcI2cInternIntCb.pfnTxRxCb = pstcIntCb->pfnTxRxCb; 03537 pstcI2c->IBCR_f.INTE = 1; 03538 } 03539 03540 if(pstcInt->bStopDetectInt == TRUE) 03541 { 03542 pstcMfsInternData->stcI2cInternIntCb.pfnStopDetectCb = pstcIntCb->pfnStopDetectCb; 03543 pstcI2c->IBCR_f.CNDE = 1; 03544 } 03545 03546 if((pstcInt->bTxRxInt == TRUE) || (pstcInt->bStopDetectInt == TRUE) || 03547 (pstcInt->bTxInt == TRUE) || (pstcInt->bTxFifoInt == TRUE) || 03548 (pstcInt->bTxIdle == TRUE) ) 03549 { 03550 Mfs_InitIrq(enIndex, TRUE); 03551 } 03552 03553 if(pstcInt->bRxInt == TRUE) 03554 { 03555 Mfs_InitIrq(enIndex, FALSE); 03556 } 03557 03558 return Ok; 03559 } 03560 03580 en_result_t Mfs_I2c_DisableInt(volatile stc_mfsn_i2c_t* pstcI2c, 03581 stc_i2c_int_sel_t* pstcInt) 03582 { 03583 stc_mfs_intern_data_t* pstcMfsInternData; 03584 en_mfs_instance_index_t enIndex; 03585 uint8_t u8Ch; 03586 03587 /* Check for valid pointer and get pointer to internal data struct ... */ 03588 pstcMfsInternData = MfsI2cGetInternDataPtr(pstcI2c); 03589 enIndex = MfsI2cGetInstanceIndex(pstcI2c); 03590 03591 if ((NULL == pstcMfsInternData) || 03592 (NULL == pstcInt) || 03593 (MfsInstanceIndexUnknown == enIndex) ) 03594 { 03595 return (ErrorInvalidParameter); 03596 } 03597 03598 u8Ch = I2cInstanceToIndex(pstcI2c); 03599 03600 if(pstcInt->bTxInt == TRUE) 03601 { 03602 pstcMfsInternData->stcI2cInternIntCb.pfnTxIntCb = NULL; 03603 pstcI2c->SMR_f.TIE = 0; 03604 } 03605 03606 if(pstcInt->bRxInt == TRUE) 03607 { 03608 pstcMfsInternData->stcI2cInternIntCb.pfnRxIntCb = NULL; 03609 pstcI2c->SMR_f.RIE = 0; 03610 } 03611 03612 if(pstcInt->bTxFifoInt == TRUE) 03613 { 03614 pstcMfsInternData->stcI2cInternIntCb.pfnTxFifoIntCb = NULL; 03615 pstcI2c->FCR1_f.FTIE = 0; 03616 } 03617 03618 if(pstcInt->bTxIdle == TRUE) 03619 { 03620 pstcMfsInternData->stcI2cInternIntCb.pfnTxIdleCb = NULL; 03621 pstcI2c->SSR_f.TBIE = 0; 03622 } 03623 03624 if(pstcInt->bTxRxInt == TRUE) 03625 { 03626 pstcMfsInternData->stcI2cInternIntCb.pfnTxRxCb = NULL; 03627 pstcI2c->IBCR_f.INTE = 0; 03628 } 03629 03630 if(pstcInt->bStopDetectInt == TRUE) 03631 { 03632 pstcMfsInternData->stcI2cInternIntCb.pfnStopDetectCb = NULL; 03633 pstcI2c->IBCR_f.CNDE = 0; 03634 } 03635 03636 // Only when TX and RX interrupts and DMA interrupt(share same IRQ with MFS ch.14, ch.15) 03637 // are all disabled, disable TX IRQ 03638 do 03639 { 03640 if(pstcI2c->IBCR_f.INTE == 1) 03641 { 03642 break; 03643 } 03644 03645 if(pstcI2c->IBCR_f.CNDE == 1) 03646 { 03647 break; 03648 } 03649 03650 if(pstcI2c->SMR_f.TIE == 1) 03651 { 03652 break; 03653 } 03654 03655 if(pstcI2c->SMR_f.RIE == 1) 03656 { 03657 break; 03658 } 03659 03660 if(pstcI2c->SSR_f.TBIE == 1) 03661 { 03662 break; 03663 } 03664 03665 if(pstcI2c->FCR1_f.FTIE == 1) 03666 { 03667 break; 03668 } 03669 03670 if(u8Ch == 14u) 03671 { 03672 if((FM0P_DMAC->DMACB1_f.CI == 1) || (FM0P_DMAC->DMACB1_f.EI == 1)) 03673 { 03674 break; 03675 } 03676 } 03677 03678 if(u8Ch == 15u) 03679 { 03680 if((FM0P_DMAC->DMACB3_f.CI == 1) || (FM0P_DMAC->DMACB3_f.EI == 1)) 03681 { 03682 break; 03683 } 03684 } 03685 03686 Mfs_DeInitIrq(enIndex, TRUE); 03687 03688 }while(0); 03689 03690 return Ok; 03691 } 03692 03693 #endif 03694 03712 en_result_t Mfs_I2c_Init(volatile stc_mfsn_i2c_t* pstcI2c, 03713 const stc_mfs_i2c_config_t* pstcConfig) 03714 { 03715 stc_mfs_intern_data_t* pstcMfsInternData; 03716 03717 /* Preset local register variables to zero */ 03718 stc_mfs_i2c_smr_field_t stcSMR = { 0 }; 03719 stc_mfs_i2c_ibcr_field_t stcIBCR = { 0 }; 03720 stc_mfs_i2c_isba_field_t stcISBA = { 0 }; 03721 stc_mfs_i2c_ismk_field_t stcISMK = { 0 }; 03722 03723 /* Check for valid pointer and get pointer to internal data struct ... */ 03724 pstcMfsInternData = MfsI2cGetInternDataPtr(pstcI2c); 03725 03726 /* Parameter check and get ptr to internal data struct */ 03727 if ((NULL == pstcMfsInternData) 03728 || (NULL == pstcConfig) 03729 ) 03730 { 03731 return (ErrorInvalidParameter); 03732 } 03733 03734 /* Set the MFS mode in the internal structure */ 03735 pstcMfsInternData->enMode = MfsI2cMode; 03736 03737 /* Set I2C mode */ 03738 switch (pstcConfig->enMsMode) 03739 { 03740 case I2cMaster: 03741 case I2cSlave: 03742 stcSMR.MD = 4u; 03743 break; 03744 default: 03745 return (ErrorInvalidParameter); 03746 } 03747 03748 /* Ack enable */ 03749 stcIBCR.ACKE = TRUE; 03750 03751 /* Slave mode */ 03752 if (I2cSlave == pstcConfig->enMsMode) 03753 { 03754 /* Set slave address */ 03755 stcISBA.SA = pstcConfig->u8SlaveAddr; 03756 /* Enable slave address detection */ 03757 stcISBA.SAEN = TRUE; 03758 /* Set slave address bit mask */ 03759 stcISMK.SM = pstcConfig->u8SlaveMaskAddr; 03760 } 03761 03762 /* Enable I2C*/ 03763 stcISMK.EN = TRUE; 03764 03765 /* now setup hardware with correct mode first and then go on with */ 03766 /* bit settings */ 03767 pstcI2c->SMR_f = stcSMR; 03768 03769 /* I2C disable before other registers are set. */ 03770 pstcI2c->ISMK = 0u; 03771 03772 /* Set baud rate generation */ 03773 (void)Mfs_I2c_SetBaudRate(pstcI2c, pstcConfig->u32BaudRate); 03774 03775 /* Set registers value */ 03776 pstcI2c->IBCR_f = stcIBCR; 03777 pstcI2c->ISBA_f = stcISBA; 03778 pstcI2c->ISMK_f = stcISMK; 03779 03780 /* Use DMA or not */ 03781 if(pstcConfig->bDmaEnable == TRUE) 03782 { 03783 pstcI2c->SSR_f.DMA = 1; 03784 } 03785 else 03786 { 03787 pstcI2c->SSR_f.DMA = 0; 03788 } 03789 03790 if(pstcConfig->bEnableFifo == TRUE) /* Use FIFO function? */ 03791 { 03792 /* Reset FIFO */ 03793 pstcI2c->FCR0_f.FCL1 = 1; 03794 pstcI2c->FCR0_f.FCL2 = 1; 03795 /* Enable FIFO receive Idle detection */ 03796 pstcI2c->FCR1_f.FRIIE = 1; 03797 /* Selection TX and RX FIFO */ 03798 switch(pstcConfig->stcFifoConfig.enFifoSel) 03799 { 03800 case MfsTxFifo1RxFifo2: 03801 pstcI2c->FCR1_f.FSEL = 0; 03802 break; 03803 case MfsTxFifo2RxFifo1: 03804 pstcI2c->FCR1_f.FSEL = 1; 03805 break; 03806 default: 03807 return (ErrorInvalidParameter); 03808 } 03809 /* Set FIFO count */ 03810 pstcI2c->FBYTE1 = pstcConfig->stcFifoConfig.u8ByteCount1; 03811 pstcI2c->FBYTE2 = pstcConfig->stcFifoConfig.u8ByteCount2; 03812 /* Enable FIFO */ 03813 pstcI2c->FCR0_f.FE1 = 1; 03814 pstcI2c->FCR0_f.FE2 = 1; 03815 } 03816 03817 return (Ok); 03818 } /* Mfs_I2c_Init */ 03819 03835 en_result_t Mfs_I2c_DeInit( volatile stc_mfsn_i2c_t* pstcI2c) 03836 { 03837 en_result_t enResult; 03838 stc_mfs_intern_data_t* pstcMfsInternData; 03839 03840 /* Check for valid pointer and get pointer to internal data struct ... */ 03841 pstcMfsInternData = MfsI2cGetInternDataPtr(pstcI2c); 03842 /* ... and check */ 03843 if (NULL == pstcMfsInternData) 03844 { 03845 enResult = ErrorInvalidParameter; 03846 } 03847 else 03848 { 03849 /* Disable I2C */ 03850 pstcI2c->ISMK_f.EN = FALSE; 03851 03852 /* Serial Mode Register clear all bits (valid in any mode) */ 03853 pstcI2c->SMR = 0u; 03854 03855 /* Reset Mfs receive and transmit bit to default */ 03856 /* and clear all error flags */ 03857 pstcI2c->IBCR = 0u; 03858 03859 /* Clear reception Errors */ 03860 pstcI2c->SSR_f.REC = TRUE; 03861 03862 /* Reset all other used register to default value */ 03863 pstcI2c->SSR = 0u; 03864 pstcI2c->IBSR = 0u; 03865 pstcI2c->FCR0 = 0u; 03866 pstcI2c->FCR1 = 0u; 03867 03868 enResult = Ok; 03869 } 03870 03871 return (enResult); 03872 } /* Mfs_I2c_DeInit */ 03873 03890 en_result_t Mfs_I2c_SetBaudRate(volatile stc_mfsn_i2c_t* pstcI2c, 03891 uint32_t u32BaudRate) 03892 { 03893 uint32_t u32Pclk1; 03894 boolean_t bTempBit = FALSE; 03895 03896 if ((NULL == pstcI2c) || (u32BaudRate > 400000)) 03897 { 03898 return ErrorInvalidParameter; 03899 } 03900 03901 bTempBit = pstcI2c->ISMK_f.EN; 03902 pstcI2c->ISMK_f.EN = 1; 03903 u32Pclk1 = __HCLK/(1ul << (APBC1_PSR_Val & 0x03u)); /* MFS is attached on APB1 bus */ 03904 pstcI2c->BGR_f.BGR = (u32Pclk1/u32BaudRate) - 1; 03905 pstcI2c->ISMK_f.EN = bTempBit; 03906 03907 return Ok; 03908 } 03909 03921 en_result_t Mfs_I2c_GenerateStart(volatile stc_mfsn_i2c_t* pstcI2c) 03922 { 03923 uint32_t u32TimeOut = SystemCoreClock; 03924 03925 if (NULL == pstcI2c) 03926 { 03927 return ErrorInvalidParameter; 03928 } 03929 03930 pstcI2c->IBCR_f.MSS = 1; 03931 while(u32TimeOut--) 03932 { 03933 if((pstcI2c->IBCR_f.MSS == 1) && (pstcI2c->IBCR_f.ACT_SCC == 1)) 03934 { 03935 return Ok; 03936 } 03937 } 03938 03939 return ErrorTimeout; 03940 } 03941 03953 en_result_t Mfs_I2c_GenerateRestart(volatile stc_mfsn_i2c_t* pstcI2c) 03954 { 03955 uint32_t u32TimeOut = SystemCoreClock; 03956 03957 if (NULL == pstcI2c) 03958 { 03959 return ErrorInvalidParameter; 03960 } 03961 03962 pstcI2c->IBCR_f.ACT_SCC = 1; 03963 03964 while(u32TimeOut--) 03965 { 03966 if(pstcI2c->IBSR_f.RSC == 1) 03967 { 03968 return Ok; 03969 } 03970 } 03971 03972 return ErrorTimeout; 03973 } 03974 03986 en_result_t Mfs_I2c_GenerateStop(volatile stc_mfsn_i2c_t* pstcI2c) 03987 { 03988 uint32_t u32TimeOut = SystemCoreClock; 03989 03990 if (NULL == pstcI2c) 03991 { 03992 return ErrorInvalidParameter; 03993 } 03994 03995 while(u32TimeOut--) 03996 { 03997 pstcI2c->IBCR &= ~0xc1u; 03998 if((pstcI2c->IBCR_f.MSS == 0) && (pstcI2c->IBCR_f.ACT_SCC == 0)) 03999 { 04000 return Ok; 04001 } 04002 } 04003 04004 return ErrorTimeout; 04005 } 04006 04019 en_result_t Mfs_I2c_SendData(volatile stc_mfsn_i2c_t* pstcI2c, uint8_t u8Data) 04020 { 04021 if (NULL == pstcI2c) 04022 { 04023 return ErrorInvalidParameter; 04024 } 04025 04026 pstcI2c->TDR = u8Data; 04027 04028 return Ok; 04029 } 04030 04040 uint8_t Mfs_I2c_ReceiveData(volatile stc_mfsn_i2c_t* pstcI2c) 04041 { 04042 return pstcI2c->RDR; 04043 } 04044 04061 en_result_t Mfs_I2c_ConfigAck(volatile stc_mfsn_i2c_t* pstcI2c, en_i2c_ack_t enAck) 04062 { 04063 stc_mfs_i2c_ibcr_field_t stcIbcr = pstcI2c->IBCR_f; 04064 04065 if (NULL == pstcI2c) 04066 { 04067 return ErrorInvalidParameter; 04068 } 04069 04070 (enAck == I2cAck) ? (stcIbcr.ACKE = 1u) : (stcIbcr.ACKE = 0u); 04071 04072 stcIbcr.ACT_SCC = 0; /* Set SCC = 0 to avoid generating a restart */ 04073 04074 pstcI2c->IBCR_f = stcIbcr; 04075 04076 return Ok; 04077 04078 } 04079 04092 en_i2c_ack_t Mfs_I2c_GetAck(volatile stc_mfsn_i2c_t* pstcI2c) 04093 { 04094 en_i2c_ack_t enRet; 04095 04096 enRet = (pstcI2c->IBSR_f.RACK == 0u) ? I2cAck : I2cNAck; 04097 04098 return enRet; 04099 } 04100 04146 boolean_t Mfs_I2c_GetStatus(volatile stc_mfsn_i2c_t* pstcI2c, 04147 en_i2c_status_t enStatus) 04148 { 04149 boolean_t bRet; 04150 04151 switch(enStatus) 04152 { 04153 case I2cOverrunError: 04154 bRet = (pstcI2c->SSR_f.ORE == 1) ? TRUE : FALSE; 04155 break; 04156 case I2cRxFull: 04157 bRet = (pstcI2c->SSR_f.RDRF == 1) ? TRUE : FALSE; 04158 break; 04159 case I2cTxEmpty: 04160 bRet = (pstcI2c->SSR_f.TDRE == 1) ? TRUE : FALSE; 04161 break; 04162 case I2cTxIdle: 04163 bRet = (pstcI2c->SSR_f.TBI == 1) ? TRUE : FALSE; 04164 break; 04165 case I2cTxFifoRequest: 04166 bRet = (pstcI2c->FCR1_f.FDRQ == 1) ? TRUE : FALSE; 04167 break; 04168 case I2cFirstByteDetect: 04169 bRet = (pstcI2c->IBSR_f.FBT == 1) ? TRUE : FALSE; 04170 break; 04171 case I2cReservedByteDetect: 04172 bRet = (pstcI2c->IBSR_f.RSA == 1) ? TRUE : FALSE; 04173 break; 04174 case I2cStopDetect: 04175 bRet = (pstcI2c->IBSR_f.SPC == 1) ? TRUE : FALSE; 04176 break; 04177 case I2cBusStatus: 04178 bRet = (pstcI2c->IBSR_f.BB == 1) ? TRUE : FALSE; 04179 break; 04180 case I2cBusErr: 04181 bRet = (pstcI2c->IBCR_f.BER == 1) ? TRUE : FALSE; 04182 break; 04183 case I2cRxTxInt: 04184 bRet = (pstcI2c->IBCR_f.INT == 1) ? TRUE : FALSE; 04185 break; 04186 case I2cDevAddrMatch: 04187 if((pstcI2c->IBCR_f.MSS == 0) && (pstcI2c->IBCR_f.ACT_SCC == 1)) 04188 { 04189 bRet = TRUE; 04190 } 04191 else 04192 { 04193 bRet = FALSE; 04194 } 04195 break; 04196 default: 04197 break; 04198 } 04199 04200 return bRet; 04201 } 04202 04203 04235 en_result_t Mfs_I2c_ClrStatus(volatile stc_mfsn_i2c_t* pstcI2c, 04236 en_i2c_status_t enStatus) 04237 { 04238 if (NULL == pstcI2c) 04239 { 04240 return ErrorInvalidParameter; 04241 } 04242 04243 switch(enStatus) 04244 { 04245 case I2cOverrunError: 04246 pstcI2c->SSR_f.REC = 1; 04247 break; 04248 case I2cRxFull: 04249 case I2cTxEmpty: 04250 case I2cTxIdle: 04251 case I2cDevAddrMatch: 04252 break; 04253 case I2cTxFifoRequest: 04254 pstcI2c->FCR1_f.FDRQ = 0u; 04255 break; 04256 case I2cFirstByteDetect: 04257 break; 04258 case I2cReservedByteDetect: 04259 break; 04260 case I2cStopDetect: 04261 pstcI2c->IBSR_f.SPC = 0u; 04262 break; 04263 case I2cBusStatus: 04264 break; 04265 case I2cBusErr: 04266 break; 04267 case I2cRxTxInt: 04268 //pstcI2c->IBCR_f.INT = 0; 04269 pstcI2c->IBCR &= ~0x41u; 04270 break; 04271 default: 04272 return ErrorInvalidParameter; 04273 } 04274 04275 return Ok; 04276 } 04277 04291 en_i2c_data_dir_t Mfs_I2c_GetDataDir(volatile stc_mfsn_i2c_t* pstcI2c) 04292 { 04293 en_i2c_data_dir_t enDir; 04294 04295 (pstcI2c->IBSR_f.TRX == 0) ? (enDir = i2c_master_tx_slave_rx) : (enDir = i2c_slave_tx_master_rx); 04296 04297 return enDir; 04298 } 04299 04312 en_result_t Mfs_I2c_ResetFifo (volatile stc_mfsn_i2c_t* pstcI2c, 04313 en_mfs_fifo_t enFifo) 04314 { 04315 if (NULL == pstcI2c) 04316 { 04317 return ErrorInvalidParameter; 04318 } 04319 04320 switch(enFifo) 04321 { 04322 case MfsFifo1: 04323 pstcI2c->FCR0_f.FCL1 = 1; 04324 break; 04325 case MfsFifo2: 04326 pstcI2c->FCR0_f.FCL2 = 1; 04327 break; 04328 default: 04329 return ErrorInvalidParameter; 04330 } 04331 04332 return Ok; 04333 } 04334 04348 en_result_t Mfs_I2c_SetFifoCount(volatile stc_mfsn_i2c_t* pstcI2c, 04349 en_mfs_fifo_t enFifo, 04350 uint8_t u8Count) 04351 { 04352 if (NULL == pstcI2c) 04353 { 04354 return ErrorInvalidParameter; 04355 } 04356 04357 switch(enFifo) 04358 { 04359 case MfsFifo1: 04360 pstcI2c->FBYTE1 = u8Count; 04361 break; 04362 case MfsFifo2: 04363 pstcI2c->FBYTE2 = u8Count; 04364 break; 04365 default: 04366 return ErrorInvalidParameter; 04367 } 04368 04369 return Ok; 04370 } 04371 04386 uint8_t Mfs_I2c_GetFifoCount(volatile stc_mfsn_i2c_t* pstcI2c, 04387 en_mfs_fifo_t enFifo) 04388 { 04389 uint8_t u8FifoCnt = 0xFFu; 04390 04391 switch(enFifo) 04392 { 04393 case MfsFifo1: 04394 u8FifoCnt = pstcI2c->FBYTE1; 04395 break; 04396 case MfsFifo2: 04397 u8FifoCnt = pstcI2c->FBYTE2; 04398 break; 04399 default: 04400 break; 04401 } 04402 04403 return u8FifoCnt; 04404 } 04405 04406 /****************************************************************************** 04407 * LIN driver functions 04408 ******************************************************************************/ 04409 04419 static stc_mfs_intern_data_t* MfsLinGetInternDataPtr(volatile stc_mfsn_lin_t* pstcLin) 04420 { 04421 stc_mfs_intern_data_t* pstcInternDataPtr = NULL; 04422 uint32_t u32Instance; 04423 04424 if (NULL != pstcLin) 04425 { 04426 for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) 04427 { 04428 if (pstcLin == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcLinInstance) 04429 { 04430 pstcInternDataPtr = &m_astcMfsInstanceDataLut[u32Instance].stcInternData; 04431 break; 04432 } 04433 } 04434 04435 } 04436 04437 return (pstcInternDataPtr); 04438 } /* MfsGetInternDataPtr */ 04439 04440 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ 04441 (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ 04442 (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ 04443 (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ 04444 (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ 04445 (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ 04446 (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ 04447 (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 04448 04457 static en_mfs_instance_index_t MfsLinGetInstanceIndex(volatile stc_mfsn_lin_t* pstcLin) 04458 { 04459 en_mfs_instance_index_t enInstanceIndex = MfsInstanceIndexUnknown; 04460 uint32_t u32Instance; 04461 04462 if (NULL != pstcLin) 04463 { 04464 for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) 04465 { 04466 if (pstcLin == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcLinInstance) 04467 { 04468 enInstanceIndex = m_astcMfsInstanceDataLut[u32Instance].stcInternData.enIndex; 04469 break; 04470 } 04471 } 04472 04473 } 04474 04475 return (enInstanceIndex); 04476 } /* MfsLinGetInstanceIndex */ 04477 04488 void MfsLinIrqHandlerRx( volatile stc_mfsn_lin_t* pstcLin, 04489 stc_mfs_intern_data_t* pstcMfsInternData) 04490 { 04491 if ((NULL != pstcLin) && (NULL != pstcMfsInternData)) 04492 { 04493 if (NULL != pstcMfsInternData->stcLinInternIntCb.pfnRxIntCb) 04494 { 04495 pstcMfsInternData->stcLinInternIntCb.pfnRxIntCb(); 04496 } 04497 } 04498 } /* MfsIrqHandlerRx */ 04499 04510 void MfsLinIrqHandlerTx( volatile stc_mfsn_lin_t* pstcLin, 04511 stc_mfs_intern_data_t* pstcMfsInternData) 04512 { 04513 if ((NULL != pstcLin) && (NULL != pstcMfsInternData)) 04514 { 04515 if(pstcLin->SSR_f.TDRE == 1) 04516 { 04517 if (NULL != pstcMfsInternData->stcLinInternIntCb.pfnTxIntCb) 04518 { 04519 pstcMfsInternData->stcLinInternIntCb.pfnTxIntCb(); 04520 } 04521 } 04522 04523 if(pstcLin->SSR_f.TBI == 1) 04524 { 04525 if (NULL != pstcMfsInternData->stcLinInternIntCb.pfnTxIdleIntCb) 04526 { 04527 pstcMfsInternData->stcLinInternIntCb.pfnTxIdleIntCb(); 04528 } 04529 } 04530 04531 if(pstcLin->FCR1_f.FDRQ == 1) 04532 { 04533 if (NULL != pstcMfsInternData->stcLinInternIntCb.pfnTxFifoIntCb) 04534 { 04535 pstcMfsInternData->stcLinInternIntCb.pfnTxFifoIntCb(); 04536 } 04537 04538 pstcLin->FCR1_f.FDRQ = 0; 04539 } 04540 04541 04542 } 04543 } /* MfsIrqHandlerTx */ 04544 04555 void MfsLinIrqHandlerStatus( volatile stc_mfsn_lin_t* pstcLin, 04556 stc_mfs_intern_data_t* pstcMfsInternData) 04557 { 04558 if(pstcLin->SSR_f.LBD == 1) 04559 { 04560 pstcLin->SSR_f.LBD = 0; 04561 if (NULL != pstcMfsInternData->stcLinInternIntCb.pfnLinBreakIntCb) 04562 { 04563 pstcMfsInternData->stcLinInternIntCb.pfnLinBreakIntCb(); 04564 } 04565 } 04566 } 04567 04589 en_result_t Mfs_Lin_EnableInt(volatile stc_mfsn_lin_t* pstcLin, 04590 stc_lin_int_sel_t* pstcInt, 04591 stc_lin_int_cb_t* pstcIntCb) 04592 { 04593 stc_mfs_intern_data_t* pstcMfsInternData; 04594 en_mfs_instance_index_t enIndex; 04595 04596 /* Check for valid pointer and get pointer to internal data struct ... */ 04597 pstcMfsInternData = MfsLinGetInternDataPtr(pstcLin); 04598 enIndex = MfsLinGetInstanceIndex(pstcLin); 04599 04600 if ((NULL == pstcMfsInternData) || 04601 (NULL == pstcInt) || 04602 (NULL == pstcIntCb) || 04603 (MfsInstanceIndexUnknown == enIndex) ) 04604 { 04605 return (ErrorInvalidParameter); 04606 } 04607 04608 if(pstcInt->bRxInt == TRUE) 04609 { 04610 pstcMfsInternData->stcLinInternIntCb.pfnRxIntCb = pstcIntCb->pfnRxIntCb; 04611 pstcLin->SCR_f.RIE = 1; 04612 } 04613 04614 if(pstcInt->bTxInt == TRUE) 04615 { 04616 pstcMfsInternData->stcLinInternIntCb.pfnTxIntCb = pstcIntCb->pfnTxIntCb; 04617 pstcLin->SCR_f.TIE = 1; 04618 } 04619 04620 if(pstcInt->bTxIdle == TRUE) 04621 { 04622 pstcMfsInternData->stcLinInternIntCb.pfnTxIdleIntCb = pstcIntCb->pfnTxIdleIntCb; 04623 pstcLin->SCR_f.TBIE = 1; 04624 } 04625 04626 if(pstcInt->bTxFifoInt == TRUE) 04627 { 04628 pstcMfsInternData->stcLinInternIntCb.pfnTxFifoIntCb = pstcIntCb->pfnTxFifoIntCb; 04629 pstcLin->FCR1_f.FTIE = 1; 04630 } 04631 04632 if(pstcInt->bLinBreakInt == TRUE) 04633 { 04634 pstcMfsInternData->stcLinInternIntCb.pfnLinBreakIntCb = pstcIntCb->pfnLinBreakIntCb; 04635 pstcLin->ESCR_f.LBIE = 1; 04636 } 04637 04638 if(pstcInt->bRxInt == TRUE) 04639 { 04640 Mfs_InitIrq(enIndex, FALSE); 04641 } 04642 04643 if((pstcInt->bTxInt == TRUE) || (pstcInt->bTxIdle == TRUE) || 04644 (pstcInt->bTxFifoInt == TRUE) || (pstcInt->bLinBreakInt == TRUE)) 04645 { 04646 Mfs_InitIrq(enIndex, TRUE); 04647 } 04648 04649 return Ok; 04650 } 04651 04668 en_result_t Mfs_Lin_DisableInt(volatile stc_mfsn_lin_t* pstcLin, 04669 stc_lin_int_sel_t* pstcInt) 04670 { 04671 stc_mfs_intern_data_t* pstcMfsInternData; 04672 en_mfs_instance_index_t enIndex; 04673 uint8_t u8Ch; 04674 04675 /* Check for valid pointer and get pointer to internal data struct ... */ 04676 pstcMfsInternData = MfsLinGetInternDataPtr(pstcLin); 04677 enIndex = MfsLinGetInstanceIndex(pstcLin); 04678 04679 if ((NULL == pstcMfsInternData) || 04680 (NULL == pstcInt)) 04681 { 04682 return (ErrorInvalidParameter); 04683 } 04684 04685 u8Ch = LinInstanceToIndex(pstcLin); 04686 04687 if(pstcInt->bRxInt == TRUE) 04688 { 04689 pstcMfsInternData->stcLinInternIntCb.pfnRxIntCb = NULL; 04690 pstcLin->SCR_f.RIE = 0; 04691 } 04692 04693 if(pstcInt->bTxInt == TRUE) 04694 { 04695 pstcMfsInternData->stcLinInternIntCb.pfnTxIntCb = NULL; 04696 pstcLin->SCR_f.TIE = 0; 04697 } 04698 04699 if(pstcInt->bTxIdle == TRUE) 04700 { 04701 pstcMfsInternData->stcLinInternIntCb.pfnTxIdleIntCb = NULL; 04702 pstcLin->SCR_f.TBIE = 0; 04703 } 04704 04705 if(pstcInt->bTxFifoInt == TRUE) 04706 { 04707 pstcMfsInternData->stcLinInternIntCb.pfnTxFifoIntCb = NULL; 04708 pstcLin->FCR1_f.FTIE = 0; 04709 } 04710 04711 if(pstcInt->bLinBreakInt == TRUE) 04712 { 04713 pstcMfsInternData->stcLinInternIntCb.pfnLinBreakIntCb = NULL; 04714 pstcLin->ESCR_f.LBIE = 0; 04715 } 04716 04717 // Only when RX interrupts and DMA interrupt(share same IRQ with MFS ch.14, ch.15) 04718 // are all disabled, disable RX IRQ 04719 do 04720 { 04721 if(pstcLin->SCR_f.RIE == 1) 04722 { 04723 break; 04724 } 04725 04726 if(u8Ch == 14u) 04727 { 04728 if((FM0P_DMAC->DMACB0_f.CI == 1) || (FM0P_DMAC->DMACB0_f.EI == 1)) 04729 { 04730 break; 04731 } 04732 } 04733 04734 if(u8Ch == 15u) 04735 { 04736 if((FM0P_DMAC->DMACB2_f.CI == 1) || (FM0P_DMAC->DMACB2_f.EI == 1)) 04737 { 04738 break; 04739 } 04740 } 04741 04742 Mfs_DeInitIrq(enIndex, FALSE); 04743 04744 }while(0); 04745 04746 // Only when TX interrupts and DMA interrupt(share same IRQ with MFS ch.14, ch.15) 04747 // are all disabled, disable TX IRQ 04748 do 04749 { 04750 if(pstcLin->SCR_f.TIE == 1) 04751 { 04752 break; 04753 } 04754 04755 if(pstcLin->SCR_f.TBIE == 1) 04756 { 04757 break; 04758 } 04759 04760 if(pstcLin->FCR1_f.FTIE == 1) 04761 { 04762 break; 04763 } 04764 04765 if(pstcLin->SCR_f.LBR == 1) 04766 { 04767 break; 04768 } 04769 04770 if(u8Ch == 14u) 04771 { 04772 if((FM0P_DMAC->DMACB1_f.CI == 0) && (FM0P_DMAC->DMACB1_f.EI == 0)) 04773 { 04774 break; 04775 } 04776 } 04777 04778 if(u8Ch == 15u) 04779 { 04780 if((FM0P_DMAC->DMACB3_f.CI == 0) && (FM0P_DMAC->DMACB3_f.EI == 0)) 04781 { 04782 break; 04783 } 04784 } 04785 04786 Mfs_DeInitIrq(enIndex, TRUE); 04787 04788 }while(0); 04789 04790 return Ok; 04791 } 04792 04793 04794 04795 #endif 04796 04814 en_result_t Mfs_Lin_Init( volatile stc_mfsn_lin_t* pstcLin, 04815 const stc_mfs_lin_config_t* pstcConfig) 04816 { 04817 stc_mfs_intern_data_t* pstcMfsInternData; 04818 uint32_t u32DummyCnt = 100; 04819 04820 /* Preset local register variables to zero */ 04821 stc_mfs_lin_smr_field_t stcSMR = { 0 }; 04822 stc_mfs_lin_scr_field_t stcSCR = { 0 }; 04823 stc_mfs_lin_escr_field_t stcESCR = { 0 }; 04824 04825 /* Check for valid pointer and get pointer to internal data struct ... */ 04826 pstcMfsInternData = MfsLinGetInternDataPtr(pstcLin); 04827 04828 /* Parameter check and get ptr to internal data struct */ 04829 if ((NULL == pstcMfsInternData) 04830 || (NULL == pstcConfig) 04831 ) 04832 { 04833 return (ErrorInvalidParameter); 04834 } 04835 04836 /* Set MFS mode in the internal structure */ 04837 pstcMfsInternData->enMode = MfsLinMode; 04838 04839 /* First of all set MFS to Asynchronous mode 0 */ 04840 pstcLin->SMR = 0u; 04841 04842 /* Then we disable TX and RX for safe operation */ 04843 pstcLin->SCR = 0u; 04844 04845 /* Clear MFS by setting the Software Reset bit */ 04846 pstcLin->SCR_f.UPCL = TRUE; 04847 04848 /* Set LIN mode to HW and preset variable */ 04849 stcSMR.MD = 3u; 04850 04851 /* Enable serial output */ 04852 stcSMR.SOE = TRUE; 04853 04854 /* Operation Mode Selection */ 04855 switch (pstcConfig->enMsMode) 04856 { 04857 /* Master */ 04858 case LinMasterMode: 04859 stcSCR.MS = FALSE; 04860 break; 04861 /* Slave */ 04862 case LinSlaveMode: 04863 stcSCR.MS = TRUE; 04864 break; 04865 default: 04866 return (ErrorInvalidParameter); 04867 } 04868 04869 /* Set LIN master configuration */ 04870 if (LinMasterMode == pstcConfig->enMsMode) 04871 { 04872 /* Stop bits configuration */ 04873 switch (pstcConfig->enStopBits) 04874 { 04875 case LinOneStopBit: 04876 stcSMR.SBL = FALSE; 04877 stcESCR.ESBL = FALSE; 04878 break; 04879 case LinTwoStopBits: 04880 stcSMR.SBL = TRUE; 04881 stcESCR.ESBL = FALSE; 04882 break; 04883 case LinThreeStopBits: 04884 stcSMR.SBL = FALSE; 04885 stcESCR.ESBL = TRUE; 04886 break; 04887 case LinFourStopBits: 04888 stcSMR.SBL = TRUE; 04889 stcESCR.ESBL = TRUE; 04890 break; 04891 default: 04892 return (ErrorInvalidParameter); 04893 } 04894 /* Break length configuration */ 04895 switch (pstcConfig->enBreakLength) 04896 { 04897 case LinBreakLength13: 04898 stcESCR.LBL = 0u; 04899 break; 04900 case LinBreakLength14: 04901 stcESCR.LBL = 1u; 04902 break; 04903 case LinBreakLength15: 04904 stcESCR.LBL = 2u; 04905 break; 04906 case LinBreakLength16: 04907 stcESCR.LBL = 3u; 04908 break; 04909 default: 04910 return (ErrorInvalidParameter); 04911 } 04912 /* Delimiter length configuration */ 04913 switch (pstcConfig->enDelimiterLength) 04914 { 04915 case LinDelimiterLength1: 04916 stcESCR.DEL = 0u; 04917 break; 04918 case LinDelimiterLength2: 04919 stcESCR.DEL = 1u; 04920 break; 04921 case LinDelimiterLength3: 04922 stcESCR.DEL = 2u; 04923 break; 04924 case LinDelimiterLength4: 04925 stcESCR.DEL = 3u; 04926 break; 04927 default: 04928 return (ErrorInvalidParameter); 04929 } 04930 } 04931 04932 /* Set Baudrate */ 04933 (void)Mfs_Lin_SetBaudRate(pstcLin, pstcConfig->u32BaudRate); 04934 04935 /* Set registers value */ 04936 pstcLin->SMR_f = stcSMR; 04937 pstcLin->SCR_f = stcSCR; 04938 pstcLin->ESCR_f = stcESCR; 04939 04940 while(u32DummyCnt--) 04941 { 04942 pstcLin->SSR_f.LBD = 0; 04943 } 04944 04945 if(pstcConfig->bEnableFifo == TRUE) 04946 { 04947 /* Reset FIFO */ 04948 pstcLin->FCR0_f.FCL1 = 1; 04949 pstcLin->FCR0_f.FCL2 = 1; 04950 /* Enable FIFO receive Idle detection */ 04951 pstcLin->FCR1_f.FRIIE = 1; 04952 /* Selection TX and RX FIFO */ 04953 switch(pstcConfig->stcFifoConfig.enFifoSel) 04954 { 04955 case MfsTxFifo1RxFifo2: 04956 pstcLin->FCR1_f.FSEL = 0; 04957 break; 04958 case MfsTxFifo2RxFifo1: 04959 pstcLin->FCR1_f.FSEL = 1; 04960 break; 04961 default: 04962 return (ErrorInvalidParameter); 04963 } 04964 /* Set FIFO count */ 04965 pstcLin->FBYTE1 = pstcConfig->stcFifoConfig.u8ByteCount1; 04966 pstcLin->FBYTE2 = pstcConfig->stcFifoConfig.u8ByteCount2; 04967 /* Enable FIFO */ 04968 pstcLin->FCR0_f.FE1 = 1; 04969 pstcLin->FCR0_f.FE2 = 1; 04970 } 04971 04972 return (Ok); 04973 } /* Mfs_Lin_Init */ 04974 04990 en_result_t Mfs_Lin_DeInit(volatile stc_mfsn_lin_t* pstcLin) 04991 { 04992 en_result_t enResult; 04993 stc_mfs_intern_data_t* pstcMfsInternData; 04994 04995 /* Check for valid pointer and get pointer to internal data struct ... */ 04996 pstcMfsInternData = MfsLinGetInternDataPtr(pstcLin); 04997 /* ... and check */ 04998 if (NULL == pstcMfsInternData) 04999 { 05000 enResult = ErrorInvalidParameter; 05001 } 05002 else 05003 { 05004 pstcLin->SCR_f.TXE = FALSE; 05005 pstcLin->SCR_f.RXE = FALSE; 05006 05007 /* Baud Rate Generation Reload Reset */ 05008 pstcLin->BGR = 0u; 05009 05010 /* Serial Mode Register clear all bits (valid in any mode) */ 05011 pstcLin->SMR = 0u; 05012 05013 /* Reset Mfs receive and transmit bit to default */ 05014 /* and clear all error flags */ 05015 pstcLin->SCR = 0u; 05016 05017 /* Clear reception Errors */ 05018 pstcLin->SSR_f.REC = TRUE; 05019 05020 /* Reset all other used register to default value */ 05021 pstcLin->SSR = 0u; 05022 pstcLin->ESCR = 0u; 05023 pstcLin->FCR0 = 0u; 05024 pstcLin->FCR1 = 0u; 05025 05026 /* Clear MFS by setting the Software Reset bit */ 05027 pstcLin->SCR_f.UPCL = TRUE; 05028 05029 enResult = Ok; 05030 } 05031 05032 return (enResult); 05033 } /* Mfs_Lin_DeInit */ 05034 05035 05052 en_result_t Mfs_Lin_SetBaudRate(volatile stc_mfsn_lin_t* pstcLin, 05053 uint32_t u32BaudRate) 05054 { 05055 uint32_t u32Pclk1; 05056 05057 if ((NULL == pstcLin) || (u32BaudRate < 3)) 05058 { 05059 return ErrorInvalidParameter; 05060 } 05061 05062 u32Pclk1 = __HCLK/(1ul << (APBC1_PSR_Val & 0x03u)); /* MFS is attached on APB1 bus */ 05063 05064 pstcLin->BGR_f.BGR = (u32Pclk1/u32BaudRate) - 1; 05065 05066 return Ok; 05067 } 05068 05080 en_result_t Mfs_Lin_GenerateBreakField(volatile stc_mfsn_lin_t* pstcLin) 05081 { 05082 if (NULL == pstcLin) 05083 { 05084 return ErrorInvalidParameter; 05085 } 05086 05087 pstcLin->SCR_f.LBR = 1; 05088 05089 return Ok; 05090 } 05091 05106 en_result_t Mfs_Lin_EnableFunc(volatile stc_mfsn_lin_t* pstcLin, en_lin_func_t enFunc) 05107 { 05108 if (NULL == pstcLin) 05109 { 05110 return ErrorInvalidParameter; 05111 } 05112 05113 switch(enFunc) 05114 { 05115 case LinTx: 05116 pstcLin->SCR_f.TXE = 1; 05117 break; 05118 case LinRx: 05119 pstcLin->SCR_f.RXE = 1; 05120 break; 05121 default: 05122 return ErrorInvalidParameter; 05123 } 05124 05125 return Ok; 05126 } 05127 05142 en_result_t Mfs_Lin_DisableFunc(volatile stc_mfsn_lin_t* pstcLin, en_lin_func_t enFunc) 05143 { 05144 if (NULL == pstcLin) 05145 { 05146 return ErrorInvalidParameter; 05147 } 05148 05149 switch(enFunc) 05150 { 05151 case LinTx: 05152 pstcLin->SCR_f.TXE = 0; 05153 break; 05154 case LinRx: 05155 pstcLin->SCR_f.RXE = 0; 05156 break; 05157 default: 05158 return ErrorInvalidParameter; 05159 } 05160 05161 return Ok; 05162 } 05163 05196 boolean_t Mfs_Lin_GetStatus(volatile stc_mfsn_lin_t* pstcLin, 05197 en_lin_status_t enStatus) 05198 { 05199 boolean_t bResult = FALSE; 05200 05201 switch(enStatus) 05202 { 05203 case LinFrameError: 05204 bResult = (pstcLin->SSR_f.FRE == 1) ? TRUE : FALSE; 05205 break; 05206 case LinOverrunError: 05207 bResult = (pstcLin->SSR_f.ORE == 1) ? TRUE : FALSE; 05208 break; 05209 case LinRxFull: 05210 bResult = (pstcLin->SSR_f.RDRF == 1) ? TRUE : FALSE; 05211 break; 05212 case LinTxEmpty: 05213 bResult = (pstcLin->SSR_f.TDRE == 1) ? TRUE : FALSE; 05214 break; 05215 case LinTxIdle: 05216 bResult = (pstcLin->SSR_f.TBI == 1) ? TRUE : FALSE; 05217 break; 05218 case LinBreakFlag: 05219 bResult = (pstcLin->SSR_f.LBD == 1) ? TRUE : FALSE; 05220 break; 05221 case LinTxFifoRequest: 05222 bResult = (pstcLin->FCR1_f.FDRQ == 1) ? TRUE : FALSE; 05223 break; 05224 default: 05225 break; 05226 } 05227 05228 return bResult; 05229 } 05230 05254 en_result_t Mfs_Lin_ClrStatus(volatile stc_mfsn_lin_t* pstcLin, 05255 en_lin_status_t enStatus) 05256 { 05257 if (NULL == pstcLin) 05258 { 05259 return ErrorInvalidParameter; 05260 } 05261 05262 switch(enStatus) 05263 { 05264 case LinFrameError: 05265 case LinOverrunError: 05266 pstcLin->SSR_f.REC = 1; 05267 break; 05268 case LinRxFull: 05269 case LinTxEmpty: 05270 case LinTxIdle: 05271 break; 05272 case LinBreakFlag: 05273 pstcLin->SSR_f.LBD = 0; 05274 break; 05275 case LinTxFifoRequest: 05276 pstcLin->FCR1_f.FDRQ = 0; 05277 break; 05278 default: 05279 return ErrorInvalidParameter; 05280 } 05281 05282 return Ok; 05283 } 05284 05297 en_result_t Mfs_Lin_SendData(volatile stc_mfsn_lin_t* pstcLin, uint8_t Data) 05298 { 05299 if (NULL == pstcLin) 05300 { 05301 return ErrorInvalidParameter; 05302 } 05303 05304 pstcLin->TDR = Data; 05305 05306 return Ok; 05307 } 05308 05318 uint8_t Mfs_Lin_ReceiveData(volatile stc_mfsn_lin_t* pstcLin) 05319 { 05320 return (pstcLin->RDR); 05321 } 05322 05335 en_result_t Mfs_Lin_ResetFifo (volatile stc_mfsn_lin_t* pstcLin, 05336 en_mfs_fifo_t enFifo) 05337 { 05338 if (NULL == pstcLin) 05339 { 05340 return ErrorInvalidParameter; 05341 } 05342 05343 switch(enFifo) 05344 { 05345 case MfsFifo1: 05346 pstcLin->FCR0_f.FCL1 = 1; 05347 break; 05348 case MfsFifo2: 05349 pstcLin->FCR0_f.FCL2 = 1; 05350 break; 05351 default: 05352 return ErrorInvalidParameter; 05353 } 05354 05355 return Ok; 05356 } 05357 05371 en_result_t Mfs_Lin_SetFifoCount(volatile stc_mfsn_lin_t* pstcLin, 05372 en_mfs_fifo_t enFifo, 05373 uint8_t u8Count) 05374 { 05375 if (NULL == pstcLin) 05376 { 05377 return ErrorInvalidParameter; 05378 } 05379 05380 switch(enFifo) 05381 { 05382 case MfsFifo1: 05383 pstcLin->FBYTE1 = u8Count; 05384 break; 05385 case MfsFifo2: 05386 pstcLin->FBYTE2 = u8Count; 05387 break; 05388 default: 05389 return ErrorInvalidParameter; 05390 } 05391 05392 return Ok; 05393 } 05394 05409 uint8_t Mfs_Lin_GetFifoCount(volatile stc_mfsn_lin_t* pstcLin, 05410 en_mfs_fifo_t enFifo) 05411 { 05412 uint8_t u8FifoCnt = 0xFFu; 05413 05414 switch(enFifo) 05415 { 05416 case MfsFifo1: 05417 u8FifoCnt = pstcLin->FBYTE1; 05418 break; 05419 case MfsFifo2: 05420 u8FifoCnt = pstcLin->FBYTE2; 05421 break; 05422 default: 05423 break; 05424 } 05425 05426 return u8FifoCnt; 05427 } 05428 05430 05431 #endif /* #if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) */ 05432 /******************************************************************************/ 05433 /* EOF (not truncated) */ 05434 /******************************************************************************/