![]() |
PDL for FM0+
Version1.0
Peripheral Driverl Library for FM0+
|
00001 /******************************************************************************* 00002 * Copyright (C) 2013 Spansion LLC. All Rights Reserved. 00003 * 00004 * This software is owned and published by: 00005 * Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). 00006 * 00007 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 00008 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. 00009 * 00010 * This software contains source code for use with Spansion 00011 * components. This software is licensed by Spansion to be adapted only 00012 * for use in systems utilizing Spansion components. Spansion shall not be 00013 * responsible for misuse or illegal use of this software for devices not 00014 * supported herein. Spansion is providing this software "AS IS" and will 00015 * not be responsible for issues arising from incorrect user implementation 00016 * of the software. 00017 * 00018 * SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, 00019 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 00020 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 00021 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 00022 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 00023 * WARRANTY OF NONINFRINGEMENT. 00024 * SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 00025 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 00026 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 00027 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 00028 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 00029 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 00030 * SAVINGS OR PROFITS, 00031 * EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00032 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR 00033 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 00034 * FROM, THE SOFTWARE. 00035 * 00036 * This software may be replicated in part or whole for the licensed use, 00037 * with the restriction that this Disclaimer and Copyright notice must be 00038 * included with each copy of this software, whether used in part or whole, 00039 * at all times. 00040 */ 00041 /******************************************************************************/ 00053 #ifndef __MFS_H__ 00054 #define __MFS_H__ 00055 00056 /******************************************************************************/ 00057 /* Include files */ 00058 /******************************************************************************/ 00059 #include "mcu.h" 00060 #include "pdl_user.h" 00061 00062 #if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) 00063 00064 /* C binding of definitions if building with C++ compiler */ 00065 #ifdef __cplusplus 00066 extern "C" 00067 { 00068 #endif 00069 00304 00305 /****************************************************************************** 00306 * Global type definitions 00307 ******************************************************************************/ 00308 #define stc_mfsn_uart_t FM0P_MFS_UART_TypeDef 00309 #define stc_mfsn_csio_t FM0P_MFS_CSIO_TypeDef 00310 #define stc_mfsn_i2c_t FM0P_MFS_I2C_TypeDef 00311 #define stc_mfsn_lin_t FM0P_MFS_LIN_TypeDef 00312 00313 #define UART0 (*((volatile stc_mfsn_uart_t *) FM0P_MFS0_UART_BASE)) 00314 #define UART1 (*((volatile stc_mfsn_uart_t *) FM0P_MFS1_UART_BASE)) 00315 #define UART2 (*((volatile stc_mfsn_uart_t *) FM0P_MFS2_UART_BASE)) 00316 #define UART3 (*((volatile stc_mfsn_uart_t *) FM0P_MFS3_UART_BASE)) 00317 #define UART4 (*((volatile stc_mfsn_uart_t *) FM0P_MFS4_UART_BASE)) 00318 #define UART5 (*((volatile stc_mfsn_uart_t *) FM0P_MFS5_UART_BASE)) 00319 #define UART6 (*((volatile stc_mfsn_uart_t *) FM0P_MFS6_UART_BASE)) 00320 #define UART7 (*((volatile stc_mfsn_uart_t *) FM0P_MFS7_UART_BASE)) 00321 #define UART8 (*((volatile stc_mfsn_uart_t *) FM0P_MFS8_UART_BASE)) 00322 #define UART9 (*((volatile stc_mfsn_uart_t *) FM0P_MFS9_UART_BASE)) 00323 #define UART10 (*((volatile stc_mfsn_uart_t *) FM0P_MFS10_UART_BASE)) 00324 #define UART11 (*((volatile stc_mfsn_uart_t *) FM0P_MFS11_UART_BASE)) 00325 #define UART12 (*((volatile stc_mfsn_uart_t *) FM0P_MFS12_UART_BASE)) 00326 #define UART13 (*((volatile stc_mfsn_uart_t *) FM0P_MFS13_UART_BASE)) 00327 #define UART14 (*((volatile stc_mfsn_uart_t *) FM0P_MFS14_UART_BASE)) 00328 #define UART15 (*((volatile stc_mfsn_uart_t *) FM0P_MFS15_UART_BASE)) 00329 00330 #define CSIO0 (*((volatile stc_mfsn_csio_t *) FM0P_MFS0_CSIO_BASE)) 00331 #define CSIO1 (*((volatile stc_mfsn_csio_t *) FM0P_MFS1_CSIO_BASE)) 00332 #define CSIO2 (*((volatile stc_mfsn_csio_t *) FM0P_MFS2_CSIO_BASE)) 00333 #define CSIO3 (*((volatile stc_mfsn_csio_t *) FM0P_MFS3_CSIO_BASE)) 00334 #define CSIO4 (*((volatile stc_mfsn_csio_t *) FM0P_MFS4_CSIO_BASE)) 00335 #define CSIO5 (*((volatile stc_mfsn_csio_t *) FM0P_MFS5_CSIO_BASE)) 00336 #define CSIO6 (*((volatile stc_mfsn_csio_t *) FM0P_MFS6_CSIO_BASE)) 00337 #define CSIO7 (*((volatile stc_mfsn_csio_t *) FM0P_MFS7_CSIO_BASE)) 00338 #define CSIO8 (*((volatile stc_mfsn_csio_t *) FM0P_MFS8_CSIO_BASE)) 00339 #define CSIO9 (*((volatile stc_mfsn_csio_t *) FM0P_MFS9_CSIO_BASE)) 00340 #define CSIO10 (*((volatile stc_mfsn_csio_t *) FM0P_MFS10_CSIO_BASE)) 00341 #define CSIO11 (*((volatile stc_mfsn_csio_t *) FM0P_MFS11_CSIO_BASE)) 00342 #define CSIO12 (*((volatile stc_mfsn_csio_t *) FM0P_MFS12_CSIO_BASE)) 00343 #define CSIO13 (*((volatile stc_mfsn_csio_t *) FM0P_MFS13_CSIO_BASE)) 00344 #define CSIO14 (*((volatile stc_mfsn_csio_t *) FM0P_MFS14_CSIO_BASE)) 00345 #define CSIO15 (*((volatile stc_mfsn_csio_t *) FM0P_MFS15_CSIO_BASE)) 00346 00347 #define I2C0 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS0_I2C_BASE)) 00348 #define I2C1 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS1_I2C_BASE)) 00349 #define I2C2 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS2_I2C_BASE)) 00350 #define I2C3 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS3_I2C_BASE)) 00351 #define I2C4 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS4_I2C_BASE)) 00352 #define I2C5 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS5_I2C_BASE)) 00353 #define I2C6 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS6_I2C_BASE)) 00354 #define I2C7 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS7_I2C_BASE)) 00355 #define I2C8 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS8_I2C_BASE)) 00356 #define I2C9 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS9_I2C_BASE)) 00357 #define I2C10 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS10_I2C_BASE)) 00358 #define I2C11 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS11_I2C_BASE)) 00359 #define I2C12 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS12_I2C_BASE)) 00360 #define I2C13 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS13_I2C_BASE)) 00361 #define I2C14 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS14_I2C_BASE)) 00362 #define I2C15 (*((volatile stc_mfsn_i2c_t *) FM0P_MFS15_I2C_BASE)) 00363 00364 #define LIN0 (*((volatile stc_mfsn_lin_t *) FM0P_MFS0_LIN_BASE)) 00365 #define LIN1 (*((volatile stc_mfsn_lin_t *) FM0P_MFS1_LIN_BASE)) 00366 #define LIN2 (*((volatile stc_mfsn_lin_t *) FM0P_MFS2_LIN_BASE)) 00367 #define LIN3 (*((volatile stc_mfsn_lin_t *) FM0P_MFS3_LIN_BASE)) 00368 #define LIN4 (*((volatile stc_mfsn_lin_t *) FM0P_MFS4_LIN_BASE)) 00369 #define LIN5 (*((volatile stc_mfsn_lin_t *) FM0P_MFS5_LIN_BASE)) 00370 #define LIN6 (*((volatile stc_mfsn_lin_t *) FM0P_MFS6_LIN_BASE)) 00371 #define LIN7 (*((volatile stc_mfsn_lin_t *) FM0P_MFS7_LIN_BASE)) 00372 #define LIN8 (*((volatile stc_mfsn_lin_t *) FM0P_MFS8_LIN_BASE)) 00373 #define LIN9 (*((volatile stc_mfsn_lin_t *) FM0P_MFS9_LIN_BASE)) 00374 #define LIN10 (*((volatile stc_mfsn_lin_t *) FM0P_MFS10_LIN_BASE)) 00375 #define LIN11 (*((volatile stc_mfsn_lin_t *) FM0P_MFS11_LIN_BASE)) 00376 #define LIN12 (*((volatile stc_mfsn_lin_t *) FM0P_MFS12_LIN_BASE)) 00377 #define LIN13 (*((volatile stc_mfsn_lin_t *) FM0P_MFS13_LIN_BASE)) 00378 #define LIN14 (*((volatile stc_mfsn_lin_t *) FM0P_MFS14_LIN_BASE)) 00379 #define LIN15 (*((volatile stc_mfsn_lin_t *) FM0P_MFS15_LIN_BASE)) 00380 00381 #define MFS_INSTANCE_COUNT \ 00382 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS0 == PDL_ON) + \ 00383 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS1 == PDL_ON) + \ 00384 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS2 == PDL_ON) + \ 00385 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS3 == PDL_ON) + \ 00386 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS4 == PDL_ON) + \ 00387 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS5 == PDL_ON) + \ 00388 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS6 == PDL_ON) + \ 00389 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS7 == PDL_ON) + \ 00390 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS8 == PDL_ON) + \ 00391 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS9 == PDL_ON) + \ 00392 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS10 == PDL_ON) + \ 00393 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS11 == PDL_ON) + \ 00394 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS12 == PDL_ON) + \ 00395 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS13 == PDL_ON) + \ 00396 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS14 == PDL_ON) + \ 00397 (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS15 == PDL_ON) 00398 00399 #define MFS0_DATA_REG_ADDR (uint32_t)(&FM0P_MFS0_UART->TDR) 00400 #define MFS1_DATA_REG_ADDR (uint32_t)(&FM0P_MFS1_UART->TDR) 00401 #define MFS2_DATA_REG_ADDR (uint32_t)(&FM0P_MFS2_UART->TDR) 00402 #define MFS3_DATA_REG_ADDR (uint32_t)(&FM0P_MFS3_UART->TDR) 00403 #define MFS4_DATA_REG_ADDR (uint32_t)(&FM0P_MFS4_UART->TDR) 00404 #define MFS5_DATA_REG_ADDR (uint32_t)(&FM0P_MFS5_UART->TDR) 00405 #define MFS6_DATA_REG_ADDR (uint32_t)(&FM0P_MFS6_UART->TDR) 00406 #define MFS7_DATA_REG_ADDR (uint32_t)(&FM0P_MFS7_UART->TDR) 00407 #define MFS8_DATA_REG_ADDR (uint32_t)(&FM0P_MFS8_UART->TDR) 00408 #define MFS9_DATA_REG_ADDR (uint32_t)(&FM0P_MFS9_UART->TDR) 00409 #define MFS10_DATA_REG_ADDR (uint32_t)(&FM0P_MFS10_UART->TDR) 00410 #define MFS11_DATA_REG_ADDR (uint32_t)(&FM0P_MFS11_UART->TDR) 00411 #define MFS12_DATA_REG_ADDR (uint32_t)(&FM0P_MFS12_UART->TDR) 00412 #define MFS13_DATA_REG_ADDR (uint32_t)(&FM0P_MFS13_UART->TDR) 00413 #define MFS14_DATA_REG_ADDR (uint32_t)(&FM0P_MFS14_UART->TDR) 00414 #define MFS15_DATA_REG_ADDR (uint32_t)(&FM0P_MFS15_UART->TDR) 00415 00416 /****************************************************************************** 00417 * Global type definitions 00418 ******************************************************************************/ 00419 00420 /****************************************************************************** 00421 * MFS FIFO type definitions 00422 ******************************************************************************/ 00427 typedef enum en_mfs_fifo_sel 00428 { 00429 MfsTxFifo1RxFifo2 = 0u, 00430 MfsTxFifo2RxFifo1 = 1u, 00431 } en_mfs_fifo_sel_t; 00432 00437 typedef struct stc_mfs_fifo_config 00438 { 00439 en_mfs_fifo_sel_t enFifoSel; 00440 uint8_t u8ByteCount1; 00441 uint8_t u8ByteCount2; 00442 } stc_mfs_fifo_config_t; 00443 00448 typedef enum en_mfs_fifo 00449 { 00450 MfsFifo1 = 0u, 00451 MfsFifo2 = 1u, 00452 } en_mfs_fifo_t; 00453 00454 /****************************************************************************** 00455 * UART type definitions 00456 ******************************************************************************/ 00461 typedef enum en_mfs_uart_mode 00462 { 00463 UartNormal = 0u, 00464 UartMulti = 1u, 00465 } en_uart_mode_t; 00466 00471 typedef enum en_uart_data_len 00472 { 00473 UartEightBits = 0u, 00474 UartFiveBits = 1u, 00475 UartSixBits = 2u, 00476 UartSevenBits = 3u, 00477 UartNineBits = 4u, 00478 } en_uart_data_len_t; 00479 00484 typedef enum en_uart_parity 00485 { 00486 UartParityNone = 0u, 00487 UartParityEven = 2u, 00488 UartParityOdd = 3u, 00489 } en_uart_parity_t; 00490 00495 typedef enum en_uart_stop_bit 00496 { 00497 UartOneStopBit = 0u, 00498 UartTwoStopBits = 1u, 00499 UartThreeStopBits = 2u, 00500 UartFourStopBits = 3u, 00501 } en_uart_stop_bit_t; 00502 00507 typedef enum en_uart_data_dir 00508 { 00509 UartDataLsbFirst = 0u, 00510 UartDataMsbFirst = 1u, 00511 }en_uart_data_dir_t; 00512 00517 typedef enum en_uart_func 00518 { 00519 UartTx = 0u, 00520 UartRx = 1u, 00521 00522 }en_uart_func_t; 00523 00528 typedef struct stc_uart_int_sel 00529 { 00530 boolean_t bTxInt; 00531 boolean_t bRxInt; 00532 boolean_t bTxIdle; 00533 boolean_t bTxFifoInt; 00534 00535 }stc_uart_int_sel_t; 00536 00541 typedef struct stc_uart_int_cb 00542 { 00543 func_ptr_t pfnTxIntCb; 00544 func_ptr_t pfnRxIntCb; 00545 func_ptr_t pfnTxIdleCb; 00546 func_ptr_t pfnTxFifoIntCb; 00547 00548 }stc_uart_int_cb_t; 00549 00554 typedef enum en_uart_status 00555 { 00556 UartParityError = 0u, 00557 UartFrameError = 1u, 00558 UartOverrunError = 2u, 00559 UartRxFull = 3u, 00560 UartTxEmpty = 4u, 00561 UartTxIdle = 5u, 00562 UartTxFifoRequest = 6u, 00563 00564 }en_uart_status_t; 00565 00570 typedef struct stc_mfs_uart_config 00571 { 00572 en_uart_mode_t enMode; 00573 uint32_t u32BautRate; 00574 en_uart_parity_t enParity; 00575 en_uart_stop_bit_t enStopBit; 00576 en_uart_data_len_t enDataLength; 00577 en_uart_data_dir_t enBitDirection; 00578 boolean_t bInvertData; 00579 boolean_t bHwFlow; 00580 00581 boolean_t bEnableFifo; 00582 stc_mfs_fifo_config_t stcFifoConfig; 00583 00584 } stc_mfs_uart_config_t; 00585 00586 /****************************************************************************** 00587 * CSIO type definitions 00588 ******************************************************************************/ 00593 typedef enum en_csio_ms_mode 00594 { 00595 CsioMaster = 0, 00596 CsioSlave = 1 00597 } en_csio_ms_mode_t; 00598 00603 typedef enum en_csio_act_mode 00604 { 00605 CsioActNormalMode = 0u, 00606 CsioActSpiMode = 1u, 00607 } en_csio_act_mode_t; 00608 00613 typedef enum en_csio_data_len 00614 { 00615 CsioFiveBits = 0u, 00616 CsioSixBits = 1u, 00617 CsioSevenBits = 2u, 00618 CsioEightBits = 3u, 00619 CsioNineBits = 4u, 00620 CsioTenBits = 5u, 00621 CsioElevenBits = 6u, 00622 CsioTwelveBits = 7u, 00623 CsioThirteenBits = 8u, 00624 CsioFourteenBits = 9u, 00625 CsioFifteenBits = 10u, 00626 CsioSixteenBits = 11u, 00627 } en_csio_data_len_t; 00628 00633 typedef enum en_csio_sync_wait_time 00634 { 00635 CsioSyncWaitZero = 0u, 00636 CsioSyncWaitOne = 1u, 00637 CsioSyncWaitTwo = 2u, 00638 CsioSyncWaitThree = 3u, 00639 } en_csio_sync_wait_time_t; 00640 00645 typedef enum en_csio_data_dir 00646 { 00647 CsioDataLsbFirst = 0u, 00648 CsioDataMsbFirst = 1u, 00649 }en_csio_data_dir_t; 00650 00655 typedef enum en_csio_timer_clk 00656 { 00657 CsioTimerNoDiv = 0u, 00658 CsioTimerDiv2 = 1u, 00659 CsioTimerDiv4 = 2u, 00660 CsioTimerDiv8 = 3u, 00661 CsioTimerDiv16 = 4u, 00662 CsioTimerDiv32 = 5u, 00663 CsioTimerDiv64 = 6u, 00664 CsioTimerDiv128 = 7u, 00665 CsioTimerDiv256 = 8u, 00666 00667 }en_csio_timer_clk_t; 00668 00673 typedef struct stc_csio_serial_timer 00674 { 00675 en_csio_timer_clk_t enClkDiv; 00676 uint8_t u8TransferByteCnt; 00677 uint16_t u16CompareVal; 00678 00679 }stc_csio_serial_timer_t; 00680 00685 typedef enum en_cs_pin_sel 00686 { 00687 CsPinScs0 = 0u, 00688 CsPinScs1 = 1u, 00689 CsPinScs2 = 2u, 00690 CsPinScs3 = 3u, 00691 00692 }en_cs_pin_sel_t; 00693 00699 typedef enum en_cs_pin_level 00700 { 00701 CsLowActive = 0u, 00702 CsHighActive = 1u, 00703 00704 }en_cs_pin_level_t; 00705 00710 typedef enum en_cs_timing_clk 00711 { 00712 CsClkNoDiv = 0u, 00713 CsClkDiv2 = 1u, 00714 CsClkDiv4 = 2u, 00715 CsClkDiv8 = 3u, 00716 CsClkDiv16 = 4u, 00717 CsClkDiv32 = 5u, 00718 CsClkDiv64 = 6u, 00719 00720 }en_cs_timing_clk_t; 00721 00726 typedef struct stc_csio_cs 00727 { 00728 en_cs_pin_sel_t enCsStartPin; 00729 en_cs_pin_sel_t enCsEndPin; 00730 en_cs_pin_level_t enLevel; 00731 boolean_t bActiveHold; 00732 en_cs_timing_clk_t enClkDiv; 00733 uint8_t u8CsSetupDelayTime; 00734 uint8_t u8CsHoldDelayTime; 00735 uint16_t u16CsDeselectTime; 00736 uint8_t u8Scs0TransferByteCnt; 00737 uint8_t u8Scs1TransferByteCnt; 00738 uint8_t u8Scs2TransferByteCnt; 00739 uint8_t u8Scs3TransferByteCnt; 00740 boolean_t bScs0En; 00741 boolean_t bScs1En; 00742 boolean_t bScs2En; 00743 boolean_t bScs3En; 00744 00745 }stc_csio_cs_t; 00746 00751 typedef enum en_csio_func 00752 { 00753 CsioTx = 0u, 00754 CsioRx = 1u, 00755 CsioSerialTimer = 2u, 00756 CsioCsErrOccur = 3u, 00757 00758 }en_csio_func_t; 00759 00764 typedef struct stc_csio_int_sel 00765 { 00766 boolean_t bTxInt; 00767 boolean_t bRxInt; 00768 boolean_t bTxIdle; 00769 boolean_t bTxFifoInt; 00770 boolean_t bCsErrInt; 00771 boolean_t bSerialTimerInt; 00772 00773 }stc_csio_int_sel_t; 00774 00779 typedef struct stc_csio_int_cb 00780 { 00781 func_ptr_t pfnTxIntCb; 00782 func_ptr_t pfnRxIntCb; 00783 func_ptr_t pfnTxIdleCb; 00784 func_ptr_t pfnTxFifoIntCb; 00785 func_ptr_t pfnCsErrIntCb; 00786 func_ptr_t pfnSerialTimerIntCb; 00787 00788 }stc_csio_int_cb_t; 00789 00794 typedef enum en_csio_status 00795 { 00796 CsioOverrunError, 00797 CsioRxFull, 00798 CsioTxEmpty, 00799 CsioTxIdle, 00800 CsioTxFifoRequest, 00801 CsioCsErrIntFlag, 00802 CsioTimerIntFlag, 00803 00804 }en_csio_status_t; 00805 00810 typedef struct stc_mfs_csio_config 00811 { 00812 en_csio_ms_mode_t enMsMode; 00813 uint32_t u32BaudRate; 00814 en_csio_act_mode_t enActMode; 00815 en_csio_sync_wait_time_t enSyncWaitTime; 00816 en_csio_data_len_t enDataLength; 00817 en_csio_data_dir_t enBitDirection; 00818 boolean_t bInvertClk ; 00819 00820 boolean_t bEnSyncTransfer; 00821 stc_csio_serial_timer_t stcSerialTimer; 00822 00823 boolean_t bEnChipSelection; 00824 stc_csio_cs_t stcCsConfig; 00825 00826 boolean_t bEnableFifo; 00827 stc_mfs_fifo_config_t stcFifoConfig; 00828 00829 } stc_mfs_csio_config_t; 00830 00831 /****************************************************************************** 00832 * I2C type definitions 00833 ******************************************************************************/ 00834 00839 typedef enum en_i2c_mode 00840 { 00841 I2cMaster = 0u, 00842 I2cSlave = 1u, 00843 00844 }en_i2c_mode_t; 00845 00850 typedef enum en_i2c_ack 00851 { 00852 I2cAck = 0u, 00853 I2cNAck = 1u, 00854 00855 }en_i2c_ack_t; 00856 00861 typedef struct stc_i2c_int_sel 00862 { 00863 boolean_t bTxInt; 00864 boolean_t bRxInt; 00865 boolean_t bTxIdle; 00866 boolean_t bTxFifoInt; 00867 boolean_t bTxRxInt; 00868 boolean_t bStopDetectInt; 00869 00870 }stc_i2c_int_sel_t; 00871 00876 typedef struct stc_i2c_int_cb 00877 { 00878 func_ptr_t pfnTxIntCb; 00879 func_ptr_t pfnRxIntCb; 00880 func_ptr_t pfnTxIdleCb; 00881 func_ptr_t pfnTxFifoIntCb; 00882 func_ptr_t pfnTxRxCb; 00883 func_ptr_t pfnStopDetectCb; 00884 00885 }stc_i2c_int_cb_t; 00886 00891 typedef enum en_i2c_status 00892 { 00893 I2cOverrunError = 0u, 00894 I2cRxFull = 1u, 00895 I2cTxEmpty = 2u, 00896 I2cTxIdle = 3u, 00897 I2cTxFifoRequest = 4u, 00898 I2cFirstByteDetect = 5u, 00899 I2cReservedByteDetect = 6u, 00900 I2cStopDetect = 7u, 00901 I2cBusStatus = 8u, 00902 I2cBusErr = 9u, 00903 I2cRxTxInt = 10u, 00904 I2cDevAddrMatch = 11u, 00905 }en_i2c_status_t; 00906 00911 typedef enum en_i2c_data_dir 00912 { 00913 i2c_master_tx_slave_rx = 0u, 00914 i2c_slave_tx_master_rx = 1u, 00915 00916 }en_i2c_data_dir_t; 00917 00922 typedef struct stc_mfs_i2c_config 00923 { 00924 en_i2c_mode_t enMsMode; 00925 uint32_t u32BaudRate; 00926 uint8_t u8SlaveAddr; 00927 uint8_t u8SlaveMaskAddr; 00928 boolean_t bWaitSelection; 00929 boolean_t bDmaEnable; 00930 00931 boolean_t bEnableFifo; 00932 stc_mfs_fifo_config_t stcFifoConfig; 00933 00934 } stc_mfs_i2c_config_t; 00935 00936 /****************************************************************************** 00937 * LIN type definitions 00938 ******************************************************************************/ 00943 typedef enum en_lin_ms_mode 00944 { 00945 LinMasterMode = 0u, 00946 LinSlaveMode = 1u, 00947 } en_lin_ms_mode_t; 00948 00953 typedef enum en_lin_stop_bit 00954 { 00955 LinOneStopBit = 0u, 00956 LinTwoStopBits = 1u, 00957 LinThreeStopBits = 2u, 00958 LinFourStopBits = 3u, 00959 } en_lin_stop_bit_t; 00960 00965 typedef enum en_lin_break_length 00966 { 00967 LinBreakLength13 = 0u, 00968 LinBreakLength14 = 1u, 00969 LinBreakLength15 = 2u, 00970 LinBreakLength16 = 3u, 00971 } en_lin_break_len_t; 00972 00977 typedef enum en_lin_delimiter_length 00978 { 00979 LinDelimiterLength1 = 0u, 00980 LinDelimiterLength2 = 1u, 00981 LinDelimiterLength3 = 2u, 00982 LinDelimiterLength4 = 3u, 00983 } en_lin_delimiter_len_t; 00984 00989 typedef enum en_lin_func 00990 { 00991 LinTx = 0u, 00992 LinRx = 1u, 00993 00994 }en_lin_func_t; 00995 01000 typedef struct stc_lin_int_sel 01001 { 01002 boolean_t bTxInt; 01003 boolean_t bRxInt; 01004 boolean_t bLinBreakInt; 01005 boolean_t bTxIdle; 01006 boolean_t bTxFifoInt; 01007 01008 }stc_lin_int_sel_t; 01009 01014 typedef struct stc_lin_int_cb 01015 { 01016 func_ptr_t pfnTxIntCb; 01017 func_ptr_t pfnRxIntCb; 01018 func_ptr_t pfnLinBreakIntCb; 01019 func_ptr_t pfnTxIdleIntCb; 01020 func_ptr_t pfnTxFifoIntCb; 01021 01022 }stc_lin_int_cb_t; 01023 01028 typedef enum en_lin_status 01029 { 01030 LinFrameError = 0u, 01031 LinOverrunError = 1u, 01032 LinRxFull = 2u, 01033 LinTxEmpty = 3u, 01034 LinTxIdle = 4u, 01035 LinBreakFlag = 5u, 01036 LinTxFifoRequest = 6u, 01037 01038 }en_lin_status_t; 01039 01044 typedef struct stc_mfs_lin_config 01045 { 01046 en_lin_ms_mode_t enMsMode; 01047 uint32_t u32BaudRate; 01048 en_lin_stop_bit_t enStopBits; 01049 en_lin_break_len_t enBreakLength; 01050 en_lin_delimiter_len_t enDelimiterLength; 01051 01052 boolean_t bEnableFifo; 01053 stc_mfs_fifo_config_t stcFifoConfig; 01054 01055 } stc_mfs_lin_config_t; 01056 01057 /******************************************************************************/ 01058 /* Local type definitions ('typedef') */ 01059 /******************************************************************************/ 01061 typedef enum en_mfs_instance_index 01062 { 01063 #if (PDL_PERIPHERAL_ENABLE_MFS0 == PDL_ON) 01064 MfsInstanceIndexMfs0, 01065 #endif 01066 #if (PDL_PERIPHERAL_ENABLE_MFS1 == PDL_ON) 01067 MfsInstanceIndexMfs1, 01068 #endif 01069 #if (PDL_PERIPHERAL_ENABLE_MFS2 == PDL_ON) 01070 MfsInstanceIndexMfs2, 01071 #endif 01072 #if (PDL_PERIPHERAL_ENABLE_MFS3 == PDL_ON) 01073 MfsInstanceIndexMfs3, 01074 #endif 01075 #if (PDL_PERIPHERAL_ENABLE_MFS4 == PDL_ON) 01076 MfsInstanceIndexMfs4, 01077 #endif 01078 #if (PDL_PERIPHERAL_ENABLE_MFS5 == PDL_ON) 01079 MfsInstanceIndexMfs5, 01080 #endif 01081 #if (PDL_PERIPHERAL_ENABLE_MFS6 == PDL_ON) 01082 MfsInstanceIndexMfs6, 01083 #endif 01084 #if (PDL_PERIPHERAL_ENABLE_MFS7 == PDL_ON) 01085 MfsInstanceIndexMfs7, 01086 #endif 01087 #if (PDL_PERIPHERAL_ENABLE_MFS8 == PDL_ON) 01088 MfsInstanceIndexMfs8, 01089 #endif 01090 #if (PDL_PERIPHERAL_ENABLE_MFS9 == PDL_ON) 01091 MfsInstanceIndexMfs9, 01092 #endif 01093 #if (PDL_PERIPHERAL_ENABLE_MFS10 == PDL_ON) 01094 MfsInstanceIndexMfs10, 01095 #endif 01096 #if (PDL_PERIPHERAL_ENABLE_MFS11 == PDL_ON) 01097 MfsInstanceIndexMfs11, 01098 #endif 01099 #if (PDL_PERIPHERAL_ENABLE_MFS12 == PDL_ON) 01100 MfsInstanceIndexMfs12, 01101 #endif 01102 #if (PDL_PERIPHERAL_ENABLE_MFS13 == PDL_ON) 01103 MfsInstanceIndexMfs13, 01104 #endif 01105 #if (PDL_PERIPHERAL_ENABLE_MFS14 == PDL_ON) 01106 MfsInstanceIndexMfs14, 01107 #endif 01108 #if (PDL_PERIPHERAL_ENABLE_MFS15 == PDL_ON) 01109 MfsInstanceIndexMfs15, 01110 #endif 01111 MfsInstanceIndexMax, 01112 MfsInstanceIndexUnknown = 0xFFu, 01113 01114 } en_mfs_instance_index_t; 01115 01117 typedef struct stc_mfsn 01118 { 01119 volatile stc_mfsn_uart_t* pstcUartInstance; 01120 volatile stc_mfsn_csio_t* pstcCsioInstance; 01121 volatile stc_mfsn_i2c_t* pstcI2cInstance; 01122 volatile stc_mfsn_lin_t* pstcLinInstance; 01123 }stc_mfsn_t; 01124 01126 typedef enum en_mfs_mode 01127 { 01128 MfsInitMode = 0u, 01129 MfsUartMode = 1u, 01130 MfsCsioMode = 2u, 01131 MfsI2cMode = 3u, 01132 MfsLinMode = 4u, 01133 01134 }en_mfs_mode_t; 01135 01137 typedef struct stc_mfs_intern_data 01138 { 01139 en_mfs_mode_t enMode; 01140 en_mfs_instance_index_t enIndex; 01141 union 01142 { 01143 func_ptr_t fnMfsInternIntCb[6]; 01144 stc_uart_int_cb_t stcUartInternIntCb; 01145 stc_csio_int_cb_t stcCsioInternIntCb; 01146 stc_i2c_int_cb_t stcI2cInternIntCb; 01147 stc_lin_int_cb_t stcLinInternIntCb; 01148 }; 01149 01150 } stc_mfs_intern_data_t; 01151 01153 typedef struct stc_mfs_instance_data 01154 { 01155 stc_mfsn_t stcInstance; 01156 stc_mfs_intern_data_t stcInternData; 01157 } stc_mfs_instance_data_t; 01158 01159 /******************************************************************************/ 01160 /* Global variable definitions ('extern') */ 01161 /******************************************************************************/ 01162 01164 extern stc_mfs_instance_data_t m_astcMfsInstanceDataLut[MFS_INSTANCE_COUNT]; 01165 01166 /******************************************************************************/ 01167 /* Global function prototypes (definition in C source) */ 01168 /******************************************************************************/ 01169 /* UART */ 01170 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ 01171 (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ 01172 (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ 01173 (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ 01174 (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ 01175 (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ 01176 (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ 01177 (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 01178 // Interrupt 01179 void MfsUartIrqHandlerTx(volatile stc_mfsn_uart_t* pstcUart, 01180 stc_mfs_intern_data_t* pstcMfsInternData); 01181 void MfsUartIrqHandlerRx(volatile stc_mfsn_uart_t* pstcUart, 01182 stc_mfs_intern_data_t* pstcMfsInternData); 01183 en_result_t Mfs_Uart_EnableInt(volatile stc_mfsn_uart_t* pstcUart, 01184 stc_uart_int_sel_t* pstcInt, 01185 stc_uart_int_cb_t* pstcIntCb); 01186 en_result_t Mfs_Uart_DisableInt(volatile stc_mfsn_uart_t* pstcUart, 01187 stc_uart_int_sel_t* pstcInt); 01188 #endif 01189 // Init/De-Init 01190 en_result_t Mfs_Uart_Init(volatile stc_mfsn_uart_t* pstcUart, 01191 const stc_mfs_uart_config_t* pstcConfig); 01192 en_result_t Mfs_Uart_DeInit(volatile stc_mfsn_uart_t* pstcUart); 01193 // Baud rate 01194 en_result_t Mfs_Uart_SetBaudRate(volatile stc_mfsn_uart_t* pstcUart, 01195 uint32_t u32BaudRate); 01196 // Function enable/disable 01197 en_result_t Mfs_Uart_EnableFunc(volatile stc_mfsn_uart_t* pstcUart, en_uart_func_t enFunc); 01198 en_result_t Mfs_Uart_DisableFunc(volatile stc_mfsn_uart_t* pstcUart, en_uart_func_t enFunc); 01199 // Status read/clear 01200 boolean_t Mfs_Uart_GetStatus(volatile stc_mfsn_uart_t* pstcUart, 01201 en_uart_status_t enStatus); 01202 en_result_t Mfs_Uart_ClrStatus(volatile stc_mfsn_uart_t* pstcUart, 01203 en_uart_status_t enStatus); 01204 // Data read/write 01205 en_result_t Mfs_Uart_SendData(volatile stc_mfsn_uart_t* pstcUart, uint16_t Data); 01206 uint16_t Mfs_Uart_ReceiveData(volatile stc_mfsn_uart_t* pstcUart); 01207 // FIFO 01208 en_result_t Mfs_Uart_ResetFifo (volatile stc_mfsn_uart_t* pstcUart, 01209 en_mfs_fifo_t enFifo); 01210 en_result_t Mfs_Uart_SetFifoCount(volatile stc_mfsn_uart_t* pstcUart, 01211 en_mfs_fifo_t enFifo, 01212 uint8_t u8Count); 01213 uint8_t Mfs_Uart_GetFifoCount(volatile stc_mfsn_uart_t* pstcUart, 01214 en_mfs_fifo_t enFifo); 01215 01216 /* CSIO */ 01217 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ 01218 (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ 01219 (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ 01220 (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ 01221 (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ 01222 (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ 01223 (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ 01224 (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 01225 // Interrupt 01226 void MfsCsioIrqHandlerTx(volatile stc_mfsn_csio_t* pstcCsio, 01227 stc_mfs_intern_data_t* pstcMfsInternData); 01228 void MfsCsioIrqHandlerRx(volatile stc_mfsn_csio_t* pstcCsio, 01229 stc_mfs_intern_data_t* pstcMfsInternData); 01230 void MfsCsioIrqHandlerStatus(volatile stc_mfsn_csio_t* pstcCsio, 01231 stc_mfs_intern_data_t* pstcMfsInternData); 01232 en_result_t Mfs_Csio_EnableInt(volatile stc_mfsn_csio_t* pstcCsio, 01233 stc_csio_int_sel_t* pstcInt, 01234 stc_csio_int_cb_t* pstcIntCb); 01235 en_result_t Mfs_Csio_DisableInt(volatile stc_mfsn_csio_t* pstcCsio, 01236 stc_csio_int_sel_t* pstcInt); 01237 #endif 01238 // Init/De-Init 01239 en_result_t Mfs_Csio_Init(volatile stc_mfsn_csio_t* pstcCsio, 01240 const stc_mfs_csio_config_t* pstcConfig); 01241 en_result_t Mfs_Csio_DeInit(volatile stc_mfsn_csio_t* pstcCsio); 01242 // Re-configuration 01243 en_result_t Mfs_Csio_SetBaudRate(volatile stc_mfsn_csio_t* pstcCsio, 01244 uint32_t u32BaudRate); 01245 en_result_t Mfs_Csio_SetTimerCompareValue(volatile stc_mfsn_csio_t* pstcCsio, 01246 uint16_t u16CompareValue); 01247 en_result_t Mfs_Csio_SetCsTransferByteCount(volatile stc_mfsn_csio_t* pstcCsio, 01248 en_cs_pin_sel_t enCsPin, 01249 uint8_t u8ByteCnt); 01250 en_result_t Mfs_Csio_SetCsHoldStatus(volatile stc_mfsn_csio_t* pstcCsio, 01251 boolean_t bHold); 01252 en_result_t Mfs_Csio_SetTimerTransferByteCount(volatile stc_mfsn_csio_t* pstcCsio, 01253 uint8_t u8ByteCnt); 01254 // Function enable/disable 01255 en_result_t Mfs_Csio_EnableFunc(volatile stc_mfsn_csio_t* pstcCsio, en_csio_func_t enFunc); 01256 en_result_t Mfs_Csio_DisableFunc(volatile stc_mfsn_csio_t* pstcCsio, en_csio_func_t enFunc); 01257 01258 // Status read/clear 01259 boolean_t Mfs_Csio_GetStatus(volatile stc_mfsn_csio_t* pstcCsio, 01260 en_csio_status_t enStatus); 01261 en_result_t Mfs_Csio_ClrStatus(volatile stc_mfsn_csio_t* pstcCsio, 01262 en_csio_status_t enStatus); 01263 // Data read/write 01264 en_result_t Mfs_Csio_SendData(volatile stc_mfsn_csio_t* pstcCsio, 01265 uint16_t u16Data, 01266 boolean_t bSotEn); 01267 uint16_t Mfs_Csio_ReceiveData(volatile stc_mfsn_csio_t* pstcCsio); 01268 // FIFO 01269 en_result_t Mfs_Csio_ResetFifo (volatile stc_mfsn_csio_t* pstcCsio, 01270 en_mfs_fifo_t enFifo); 01271 en_result_t Mfs_Csio_SetFifoCount(volatile stc_mfsn_csio_t* pstcCsio, 01272 en_mfs_fifo_t enFifo, 01273 uint8_t u8Count); 01274 uint8_t Mfs_Csio_GetFifoCount(volatile stc_mfsn_csio_t* pstcCsio, 01275 en_mfs_fifo_t enFifo); 01276 /* I2C */ 01277 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ 01278 (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ 01279 (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ 01280 (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ 01281 (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ 01282 (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ 01283 (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ 01284 (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 01285 // Interrupt 01286 void MfsI2cIrqHandlerTx(volatile stc_mfsn_i2c_t* pstcI2c, 01287 stc_mfs_intern_data_t* pstcMfsInternData); 01288 void MfsI2cIrqHandlerRx(volatile stc_mfsn_i2c_t* pstcI2c, 01289 stc_mfs_intern_data_t* pstcMfsInternData); 01290 void MfsI2cIrqHandlerStatus(volatile stc_mfsn_i2c_t* pstcI2c, 01291 stc_mfs_intern_data_t* pstcMfsInternData); 01292 en_result_t Mfs_I2c_EnableInt(volatile stc_mfsn_i2c_t* pstcI2c, 01293 stc_i2c_int_sel_t* pstcInt, 01294 stc_i2c_int_cb_t* pstcIntCb); 01295 en_result_t Mfs_I2c_DisableInt(volatile stc_mfsn_i2c_t* pstcI2c, 01296 stc_i2c_int_sel_t* pstcInt); 01297 #endif 01298 // Init/De-Init 01299 en_result_t Mfs_I2c_Init(volatile stc_mfsn_i2c_t* pstcI2c, 01300 const stc_mfs_i2c_config_t* pstcConfig); 01301 en_result_t Mfs_I2c_DeInit(volatile stc_mfsn_i2c_t* pstcI2c ); 01302 01303 // Start/Stop 01304 en_result_t Mfs_I2c_GenerateStart(volatile stc_mfsn_i2c_t* pstcI2c); 01305 en_result_t Mfs_I2c_GenerateRestart(volatile stc_mfsn_i2c_t* pstcI2c); 01306 en_result_t Mfs_I2c_GenerateStop(volatile stc_mfsn_i2c_t* pstcI2c); 01307 01308 // Re-configure baud rate 01309 en_result_t Mfs_I2c_SetBaudRate(volatile stc_mfsn_i2c_t* pstcI2c, 01310 uint32_t u32BaudRate); 01311 // Data read/write 01312 en_result_t Mfs_I2c_SendData(volatile stc_mfsn_i2c_t* pstcI2c, uint8_t u8Data); 01313 uint8_t Mfs_I2c_ReceiveData(volatile stc_mfsn_i2c_t* pstcI2c); 01314 01315 // ACK 01316 en_result_t Mfs_I2c_ConfigAck(volatile stc_mfsn_i2c_t* pstcI2c, en_i2c_ack_t enAck); 01317 en_i2c_ack_t Mfs_I2c_GetAck(volatile stc_mfsn_i2c_t* pstcI2c); 01318 01319 // Status read/clear 01320 boolean_t Mfs_I2c_GetStatus(volatile stc_mfsn_i2c_t* pstcI2c, 01321 en_i2c_status_t enStatus); 01322 en_result_t Mfs_I2c_ClrStatus(volatile stc_mfsn_i2c_t* pstcI2c, 01323 en_i2c_status_t enStatus); 01324 01325 // Get Data direction in slave mode 01326 en_i2c_data_dir_t Mfs_I2c_GetDataDir(volatile stc_mfsn_i2c_t* pstcI2c); 01327 01328 // FIFO 01329 en_result_t Mfs_I2c_ResetFifo (volatile stc_mfsn_i2c_t* pstcI2c, 01330 en_mfs_fifo_t enFifo); 01331 en_result_t Mfs_I2c_SetFifoCount(volatile stc_mfsn_i2c_t* pstcI2c, 01332 en_mfs_fifo_t enFifo, 01333 uint8_t u8Count); 01334 uint8_t Mfs_I2c_GetFifoCount(volatile stc_mfsn_i2c_t* pstcI2c, 01335 en_mfs_fifo_t enFifo); 01336 01337 /* LIN */ 01338 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ 01339 (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ 01340 (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ 01341 (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ 01342 (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ 01343 (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ 01344 (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ 01345 (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) 01346 // Interrupt 01347 void MfsLinIrqHandlerTx(volatile stc_mfsn_lin_t* pstcLin, 01348 stc_mfs_intern_data_t* pstcMfsInternData); 01349 void MfsLinIrqHandlerRx(volatile stc_mfsn_lin_t* pstcLin, 01350 stc_mfs_intern_data_t* pstcMfsInternData); 01351 void MfsLinIrqHandlerStatus(volatile stc_mfsn_lin_t* pstcLin, 01352 stc_mfs_intern_data_t* pstcMfsInternData); 01353 en_result_t Mfs_Lin_EnableInt(volatile stc_mfsn_lin_t* pstcLin, 01354 stc_lin_int_sel_t* pstcInt, 01355 stc_lin_int_cb_t* pstcIntCb); 01356 en_result_t Mfs_Lin_DisableInt(volatile stc_mfsn_lin_t* pstcLin, 01357 stc_lin_int_sel_t* pstcInt); 01358 #endif 01359 // Init/De-Init 01360 en_result_t Mfs_Lin_Init(volatile stc_mfsn_lin_t* pstcLin, 01361 const stc_mfs_lin_config_t* pstcConfig); 01362 en_result_t Mfs_Lin_DeInit(volatile stc_mfsn_lin_t* pstcLin); 01363 // Baud rate 01364 en_result_t Mfs_Lin_SetBaudRate(volatile stc_mfsn_lin_t* pstcLin, 01365 uint32_t u32BaudRate); 01366 // Generate break field 01367 en_result_t Mfs_Lin_GenerateBreakField(volatile stc_mfsn_lin_t* pstcLin); 01368 01369 // Function enable/disable 01370 en_result_t Mfs_Lin_EnableFunc(volatile stc_mfsn_lin_t* pstcLin, en_lin_func_t enFunc); 01371 en_result_t Mfs_Lin_DisableFunc(volatile stc_mfsn_lin_t* pstcLin, en_lin_func_t enFunc); 01372 // Status read/clear 01373 boolean_t Mfs_Lin_GetStatus(volatile stc_mfsn_lin_t* pstcLin, 01374 en_lin_status_t enStatus); 01375 en_result_t Mfs_Lin_ClrStatus(volatile stc_mfsn_lin_t* pstcLin, 01376 en_lin_status_t enStatus); 01377 // Data read/write 01378 en_result_t Mfs_Lin_SendData(volatile stc_mfsn_lin_t* pstcLin, uint8_t Data); 01379 uint8_t Mfs_Lin_ReceiveData(volatile stc_mfsn_lin_t* pstcLin); 01380 // FIFO 01381 en_result_t Mfs_Lin_ResetFifo (volatile stc_mfsn_lin_t* pstcLin, 01382 en_mfs_fifo_t enFifo); 01383 en_result_t Mfs_Lin_SetFifoCount(volatile stc_mfsn_lin_t* pstcLin, 01384 en_mfs_fifo_t enFifo, 01385 uint8_t u8Count); 01386 uint8_t Mfs_Lin_GetFifoCount(volatile stc_mfsn_lin_t* pstcLin, 01387 en_mfs_fifo_t enFifo); 01389 01390 #ifdef __cplusplus 01391 } 01392 #endif 01393 01394 #endif /* #if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) */ 01395 01396 #endif /* __MFS_H__ */ 01397 /******************************************************************************/ 01398 /* EOF (not truncated) */ 01399 /******************************************************************************/